A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

A recreational vehicle control apparatus and a recreational vehicle are provided. The recreational vehicle control apparatus includes a first controlled switch configured to generate a first output signal in response to receiving a first control signal, and switch a polarity of the first output signal based on a status of the first control signal. A second controlled switch is configured to generate a second output signal in response to receiving the first control signal. The second controlled switch outputs the second output signal to a first controlled end of a controlled object group. A third controlled switch is configured to generate a third output signal in response to receiving the second control signal and the first output signal transmitted by the first controlled switch. The third controlled switch outputs the third output signal to a second controlled end of the controlled object group. The present application may save wires and equipment with high integration level and small space occupation.

A switch device for switching an analog electrical input signal includes: a switching transistor being a flipped-well-silicon-on-insulator-NMOS transistor; and a bootstrapping arrangement including a voltage providing arrangement for providing a floating voltage during the on-state, wherein the floating voltage is provided at a positive terminal and at a negative terminal of the voltage providing arrangement; wherein the bootstrapping arrangement is configured in such way that during the on-state the positive terminal is electrically connected to the front gate contact of the switching transistor and to the back gate contact of the switching transistor, and the negative terminal is electrically connected to the source contact of the switching transistor; wherein the bootstrapping arrangement is configured in such way that during the off-state the positive terminal and the negative terminal are not electrically connected to the switching transistor.

A control circuit controlling to drive a switching device includes a first detection circuit that detects whether a power supply voltage received by a drive circuit that drives the switching device drops below a first level, a second detection circuit that receives a current flowing through the switching device and detects whether the current exceeds a first value, and an abnormality detection circuit that causes the drive circuit to turn off the switching device, based on whether a condition that the power supply voltage is lower than the first level and the current flowing through the switching device is larger than the first value is satisfied.

An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

A high temperature (HT) gate driver for Silicon Carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) uses commercial off-the-shelf COTS discrete components, and has an integrated short-circuit or overcurrent protection circuit and under voltage lock out (UVLO) protection circuit.

A transistor switching circuit and an integrated circuit thereof are provided. The transistor switching circuit includes: at least two transistors M1 and M2, and a voltage follower. The gate of the transistor M1 and the gate of the transistor M2 are connected to a first node G, the first node G is connected to a first current source, and the source of the transistor M1 and the source of the transistor M2 are connected to a second node S1. The voltage follower includes a transistor M3 and a second current source. The gate of the transistor M3 is connected to the second node S1, and the source of the transistor M3 is connected to the second current source. One end of a resistive device is connected to the source of the transistor M3, and another end of the resistive device is connected to the first node G.

An electronic device includes a multiplexer (MUX), a switching array and logic circuitry. The MUX includes multiple input ports and an output port, and is configured to receive, via the input ports, multiple input signals, and to output, via the output port, a selected signal among the input signals. The switching array is coupled to the input ports of the MUX and is configured to receive the input signals and to connect or disconnect between each input signal and a respective input port. The logic circuitry is electrically coupled to the switching array and to the MUX, and is configured to control the switching array to connect at least the selected signal that the MUX is outputting, and to disconnect all the input signals other than the at least selected signal.