A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.

A switch circuit is provided. The switch circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control end, a first output end, and a first input end. The first input end receives a first input signal whose logic level is one. The first P-type control transistor is coupled to the first input end and the first control end. The first P-type control transistor includes a second control end. The second control end receives a second input signal whose logic level is zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, the first input signal is transmitted to the first control end of the P-type transistor switch to turn off the P-type transistor switch.

According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.

In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.

A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.

An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.

Examples of a system and method are disclosed herein. An example of the system includes a first computer having a port and a first operating system to execute on the first computer. The system also includes a second computer coupled to the port of the first computer to receive power from the first computer, the second computer having a second operating system to simultaneously execute on the second computer. The system additionally includes a circuit to selectively switch between a first context supported by the first operating system of the first computer and a second context supported by the second operating system without waiting to save the first and second contexts.

A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.