A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

According to one embodiment, a semiconductor integrated circuit device includes an oscillator, a frequency divider, and a control circuit. The oscillator is configured to oscillate at a variable oscillation frequency. The frequency divider is configured to oscillate at a variable free-running oscillation frequency, and has a frequency dividing range that transitions according to a variation in the free-running oscillation frequency. The control circuit is configured to control the oscillator to vary the oscillation frequency during a calibration operation that adjusts the oscillation frequency and is configured to control the frequency divider to cause the frequency dividing range to transition based on an amount of variation of the oscillation frequency.

Circuitry for generating a compliance voltage (V+) for the current sources and/or sinks in an implantable stimulator device in disclosed. The circuitry assesses whether V+ is optimal for a given pulse, and if not, adjusts V+ for the next pulse. The circuitry uses amplifiers to measure the voltage drop across active PDACs (current sources) and NDAC (current sinks) at an appropriate time during the pulse. The measured voltages are assessed to determine whether they are high or low relative to optimal values. If low, a V+ regulator is controlled to increase V+ for the next pulse; if not, the V+ regulator is controlled to decrease V+ for the next pulse. Through this approach, gradual changes that may be occurring in the implant environment can be accounted for, with V+ adjusted on a pulse-by-pulse basis to keep the voltage drops at or near optimal levels for efficient DAC operation.

Circuitry for generating a compliance voltage (V+) for the current sources and/or sinks in an implantable stimulator device in disclosed. The circuitry assesses whether V+ is optimal for a given pulse, and if not, adjusts V+ for the next pulse. The circuitry uses amplifiers to measure the voltage drop across active PDACs (current sources) and NDAC (current sinks) at an appropriate time during the pulse. The measured voltages are assessed to determine whether they are high or low relative to optimal values. If low, a V+ regulator is controlled to increase V+ for the next pulse; if not, the V+ regulator is controlled to decrease V+ for the next pulse. Through this approach, gradual changes that may be occurring in the implant environment can be accounted for, with V+ adjusted on a pulse-by-pulse basis to keep the voltage drops at or near optimal levels for efficient DAC operation.

A voltage-controlled oscillator, including a voltage-controlled LC resonator including at least one first output node; an amplifier including at least one first dual-gate MOS transistor including first and second gates, coupling the first output node to a second node of application of a reference potential; and a regulation circuit capable of applying to the second gate of the first transistor a bias voltage variable according to the amplitude of the oscillations of a signal delivered on the first output node of the oscillator.

The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increased or decreased based upon a detected vibration level. In an embodiment, the phase locked loop includes a controllable oscillator, an output module, a filter module and a detector. The filter module can be configured to receive a bandwidth control signal to modify a bandwidth of the phase locked loop based on a vibration signal. In an embodiment, the vibration signal corresponds to a vibration level experienced by the phased locked loop. The detector can be configured to receive a PLL output signal from the output module and to receive a PLL input signal.

An integrated circuit apparatus includes an oscillation circuit that generates an oscillation signal by using a resonator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a DC voltage generation circuit that generates a DC voltage used to generate the oscillation signal or the clock signal, a power source pad to which a power source voltage is supplied, a ground pad to which a ground voltage is supplied, and a clock pad via which the clock signal is outputted. The ground pad and the DC voltage generation circuit are disposed so as to overlap with each other in the plan view.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

According to the embodiments of the present disclosure, there is provided a sensor for detecting a temperature. The sensor comprises a switch circuit; a charge/discharge circuit connected to the switch circuit, and configured to be charged and discharged under control of the switch circuit; a sensing circuit connected to the charge/discharge circuit, and configured to cause a charge/discharge period of the charge/discharge circuit to change with a temperature of the sensing circuit; and an oscillation circuit connected to the switch circuit and the charge/discharge circuit, and configured to generate, under action of the charge/discharge circuit, an oscillation signal for controlling the switch circuit, wherein an oscillation frequency of the oscillation signal is dependent on the charge/discharge period and thus indicates the temperature of the sensing circuit. In addition, the embodiments of the present disclosure further provide an array substrate and display comprising the sensor, and a corresponding voltage adjustment method.