An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.

The present disclosure provides a semiconductor circuit including: a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.

A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.

A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.