H03L7/00

Adaptive voltage converter
11249509 · 2022-02-15 ·

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

System and method for phase error compensation in synchronized devices

A system and method for compensating for detected phase errors during communications between synchronized devices. In an embodiment, the two devices may be a touch screen device and a synchronized stylus device. To this end, the touch screen device includes a controller configured to receive data signals from the stylus at specific time intervals. The touch screen device generates an internal control signal for receiving the incoming data signals at an expected frequency. The touch screen device further includes circuitry for measuring differences in the time a data signal is actually received against when the data signal was expected to be received and determines a time difference (e.g., a phase error). Then, the internal control signal may be adjusted to compensate for the accumulated phase error. Such a measurement and compensation helps ensure that communications remain in synchronization without having to reestablish synchronization through a cumbersome synchronization process.

System and method for phase error compensation in synchronized devices

A system and method for compensating for detected phase errors during communications between synchronized devices. In an embodiment, the two devices may be a touch screen device and a synchronized stylus device. To this end, the touch screen device includes a controller configured to receive data signals from the stylus at specific time intervals. The touch screen device generates an internal control signal for receiving the incoming data signals at an expected frequency. The touch screen device further includes circuitry for measuring differences in the time a data signal is actually received against when the data signal was expected to be received and determines a time difference (e.g., a phase error). Then, the internal control signal may be adjusted to compensate for the accumulated phase error. Such a measurement and compensation helps ensure that communications remain in synchronization without having to reestablish synchronization through a cumbersome synchronization process.

Semiconductor devices and semiconductor systems relating to the prevention of a potential difference between signals from being reversed
09773530 · 2017-09-26 · ·

A semiconductor device may be provided. The semiconductor device may be configured to adjust a level of a first strobe signal to a predetermined level during a first time period. The semiconductor device may be configured to adjust a swing width of the first strobe signal during a second time period.

RADIO FREQUENCY OSCILLATOR

The embodiments of the invention relate to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

TEMPERATURE COMPENSATED OSCILLATOR DRIVER

A circuit includes an oscillator having a driver and a resonator. The driver receives a supply voltage at a supply input and provides a drive output to drive the resonator to generate an oscillator output signal. A power converter receives an input voltage and generates the supply voltage to the supply input of the driver. A temperature tracking device in the power converter controls the voltage level of the supply voltage to the supply input of the driver based on temperature such that the supply voltage varies inversely to the temperature of the circuit.

SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR SUPPLYING CLOCK SIGNALS IN SEMICONDUCTOR INTEGRATED CIRCUIT
20170269630 · 2017-09-21 · ·

A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR SUPPLYING CLOCK SIGNALS IN SEMICONDUCTOR INTEGRATED CIRCUIT
20170269630 · 2017-09-21 · ·

A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

DEVICE AND METHOD FOR HANDLING CARRIER FREQUENCY OFFSET
20170325186 · 2017-11-09 ·

A communication device includes: a computing circuit, performing a J.sup.th power operation according to a first plurality of time-domain signals to generate a first plurality of computed signals; a transforming circuit, coupled to the computing circuit, transforming the first plurality of computed signals to a first plurality of frequency-domain signals according to a time-frequency transformation; a control circuit, coupled to the converting circuit, performing an absolute value operation on the first plurality of frequency-domain signals to generate a first plurality of output signals; a selecting circuit, coupled to the control circuit, selecting a maximum output signal satisfying a check condition from the first plurality of output signals; and a frequency estimating circuit, coupled to the selecting circuit, estimating a carrier frequency offset according to the maximum output signal.

DEVICE AND METHOD FOR HANDLING CARRIER FREQUENCY OFFSET
20170325186 · 2017-11-09 ·

A communication device includes: a computing circuit, performing a J.sup.th power operation according to a first plurality of time-domain signals to generate a first plurality of computed signals; a transforming circuit, coupled to the computing circuit, transforming the first plurality of computed signals to a first plurality of frequency-domain signals according to a time-frequency transformation; a control circuit, coupled to the converting circuit, performing an absolute value operation on the first plurality of frequency-domain signals to generate a first plurality of output signals; a selecting circuit, coupled to the control circuit, selecting a maximum output signal satisfying a check condition from the first plurality of output signals; and a frequency estimating circuit, coupled to the selecting circuit, estimating a carrier frequency offset according to the maximum output signal.