Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.

An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.

The invention relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal S.sub.Sensor, wherein the sensor output signal S.sub.Sensor is based on an instantaneous stress or strain component a in the semiconductor substrate, a processing arrangement for processing the sensor output signal S.sub.Sensor and providing a control signal S.sub.Control depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S.sub.osc having an oscillator frequency f.sub.osc based on the control signal S.sub.Control, wherein the control signal S.sub.Control controls the oscillator output signal S.sub.osc, and wherein the control signal S.sub.Control reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S.sub.osc, so that the oscillator circuitry provides a stress compensated oscillator output signal.

A multi-clock domain system includes a synchronizer circuit. The synchronizer circuit includes a sequential logic circuit and a synchronizing stage. The sequential logic circuit receives a functional signal that is generated based on a first clock signal that is further associated with a first clock domain, a second clock signal that is associated with a second clock domain, and a reference signal. Based on the first and second clock signals and the reference signal, the synchronizer circuit outputs a logic signal. When the functional signal is activated, the logic signal is activated and remains activated for a predetermined time duration after the functional signal is deactivated. The synchronizing stage receives the second clock signal and further receives the logic signal from the sequential logic circuit, and outputs a synchronized functional signal.

A multi-clock domain system includes a synchronizer circuit. The synchronizer circuit includes a sequential logic circuit and a synchronizing stage. The sequential logic circuit receives a functional signal that is generated based on a first clock signal that is further associated with a first clock domain, a second clock signal that is associated with a second clock domain, and a reference signal. Based on the first and second clock signals and the reference signal, the synchronizer circuit outputs a logic signal. When the functional signal is activated, the logic signal is activated and remains activated for a predetermined time duration after the functional signal is deactivated. The synchronizing stage receives the second clock signal and further receives the logic signal from the sequential logic circuit, and outputs a synchronized functional signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.