H03M3/00

Incremental analog-to-digital converter

An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.

Analog to digital converter with floating digital channel configuration

One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Sub-ranging SAR analog-to-digital converter with meta-stability detection and correction circuitry
09813073 · 2017-11-07 · ·

A sub-ranging SAR ADC has a coarse flash ADC that generates bit values corresponding to MSBs of the digital output value, and a fine SAR ADC that generates bit values corresponding to LSBs of the digital output value. The fine ADC generates successive analog approximation signals for the analog input signal. Meta-stability (MTS) detection circuitry detects a coarse-ADC MTS condition in the coarse ADC if a magnitude of a difference between a current approximation signal and a previous approximation signal is greater than a specified threshold level. A controller controls operations of the sub-ranging ADC to correct for a detected coarse-ADC MTS condition. The MTS detection circuitry includes a positive MTS detector that detects a positive coarse-ADC MTS condition in the coarse ADC and a negative MTS detector that detects a negative coarse-ADC MTS condition in the coarse ADC.

Base station and antenna calibration method
09813134 · 2017-11-07 · ·

A first FFT operator converts, with respect to each of analog circuits, a feedback signal x(t) in the time domain that is obtained after a transmission signal d(t) passes through the analog circuit into a feedback signal X(f) in the frequency domain. A second FFT operator converts the transmission signal in the time domain into a transmission signal D(f) in the frequency domain. A phase error calculator calculates, with respect to each of the analog circuits, a phase error C(f) in the frequency domain based on the feedback signal X(f) and the transmission signal D(f). An IFFT operator calculates, with respect to each of the analog circuits, a tap coefficient c(t) of an FIR filter based on the phase error C(f). The FIR filter 21 filters, with respect to each of the analog circuits, the transmission signal d(t) based on the tap coefficient c(t).

METHOD FOR PROCESSING A MEASURED-VALUE SIGNAL DETERMINED IN AN ANALOG MANNER, A RESOLVER SYSTEM FOR IMPLEMENTING THE METHOD AND A METHOD FOR DETERMINING AN OUTPUT CURRENT OF A CONVERTER
20170317687 · 2017-11-02 ·

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency f.sub.S, that is, at a clock-pulse period T.sub.S=1/f.sub.S, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency f.sub.D, that is, at a clock-pulse period T.sub.D=1/f.sub.D, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.

SIGNAL MODULATION FOR RADIOFREQUENCY COMMUNICATIONS
20170317686 · 2017-11-02 · ·

A signal modulation device comprising: an input for receiving a complex input signal (106) comprising an in-phase component signal and a quadrature-phase component signal, a sigma-delta modulator (110) for modulating the complex input signal at an oversampling clock rate (F1) into an intermediary signal (112), a numerical oscillator (60) for generating a phase signal (61) oscillating at a selected carrier frequency (FC), wherein the phase signal takes a finite number of quantized states, and a symbol mapping table (114) comprising a predefined quantized symbol for each quantized complex state of the intermediary signal and each quantized state of the phase signal, and operates at each oversampling clock period (F1) to select a quantized symbol (116) as a function of a current quantized complex state of the intermediary signal (112) and a current quantized state of the phase signal (61).

Dual-path analog to digital converter

Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal.

Apparatus having source follower based DAC inter-symbol interference cancellation

A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that includes a plurality of switches coupled to receive differential digital control signals and to provide first and second differential current outputs, a current source coupled to an upper rail and to a first node of the switching circuit, a first current sink coupled to a lower rail and to a second node of the switching circuit, and an interference cancellation circuit coupled to substantially prevent a tail capacitance current from flowing through the first and second differential current outputs.

DIGITAL MODULATION DEVICE, AND DIGITAL MODULATION METHOD
20170310338 · 2017-10-26 · ·

This invention enables to efficiently improve the signal-to-noise power ratio of a delta-sigma modulator without increasing the operating frequency. A digital modulation device 40 includes: a setting unit 41 that sets mutually different default values for N delta-sigma modulation units 42-1 to 42-N; N delta-sigma modulation units 42-1 to 42-N that input signals for each clock cycle indicated in a first clock signal and then perform delta-sigma modulation on the input signals to output modulated signals including noise signals having values that change in accordance with default values; and a serial output unit 43 that inputs, in order, the modulated signals output by the delta-sigma modulation units 42-1 to 42-N for each clock cycle indicated in a second clock signal, the second clock signal having a clock cycle that is 1/N of the clock cycle of the first clock signal, and then serializes and outputs the modulated signals.

Analog-to-digital converter (ADC) dynamic range enhancement for voice-activated systems

The dynamic range and power efficiency of a voice-activated system may be improved by dynamically adjusting the configuration of the voice-activated system's input path. In one embodiment, a first portion of audio may be received through an input path of the voice-activated system having a first configuration. A characteristic of the first portion of audio may be determined and the input path may be adjusted to a second configuration based on the determined characteristic. A second portion of audio may then be received through the input path having the second configuration, and speech analysis may be performed on the second portion of audio.