A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

There are provided a signal generation unit that generates a predetermined digital signal, a level conversion unit that converts a level of the digital signal generated by the signal generation unit, a DA converter that converts the digital signal of which the level is converted by the level conversion unit into an analog signal in a predetermined intermediate frequency bandwidth, and a control unit that creates correction data for correcting a linearity of a level of an output signal of the DA converter for all frequencies to be used, based on actual data which is data of a level of an actual output signal when a setting of the level of the output signal of the DA converter is changed at a predetermined level interval, at a predetermined frequency, and converts a level of an input signal of the DA converter with the correction data.

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Disclosed herein are devices, systems, and methods for improved demodulation. In one embodiment, a demodulator includes an input port configured to receive an analog input signal having a first frequency spectrum, a delta-sigma modulator electrically coupled with the input port, a digital downconverter electrically coupled with the delta-sigma modulator, and a filter electrically coupled with the digital downconverter. The filter is configured for a passband having a second frequency spectrum. The demodulator also includes an output port electrically coupled with the filter. The output port is configured to provide an output signal having the second frequency spectrum.

A driving circuit for controlling a MEMS oscillator includes a digital conversion stage to acquire a differential sensing signal indicative of a displacement of a movable mass of the MEMS oscillator, and to convert the differential sensing signal of analog type into a digital differential signal of digital type. Processing circuitry is configured to generate a digital control signal of digital type as a function of the comparison between the digital differential signal and a differential reference signal indicative of a target amplitude of oscillation of the movable mass which causes the resonance of the MEMS oscillator. An analog conversion stage includes a ΣΔ DAC and is configured to convert the digital control signal into a PDM control signal of analog type. A filtering stage of low-pass type, by filtering the PDM control signal, generates a control signal for controlling the amplitude of oscillation of the movable mass.

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2.sup.nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a K.sup.th sampling period, a quantization error signal for a K.sup.th period according to an internal signal, a quantization error signal for a (K−1).sup.th period, a filtered quantization error signal for the (K−1).sup.th period and a filtered quantization error signal for a (K−2).sup.th period; an integrating capacitor configured to store the quantization error signal for the K.sup.th period, to weight the internal signal in a (K+1).sup.th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the K.sup.th period in a K.sup.th discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1).sup.th sampling period and a (K+2).sup.th sampling period; and a comparator configured to quantize the quantization error signal for the K.sup.th period.

Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

The present invention relates to a sigma-delta analogue-to-digital converter. The sigma-delta analogue-to-digital converter comprises a transconductance stage having first, second and third terminals. A capacitor is connected in parallel at the third terminal. Further, the sigma-delta analogue-to-digital converter comprises a quantiser at the third terminal of the transconductance stage with feedback by a voltage digital-to-analogue converter for feeding back a feedback signal to one of the terminals of the transconductance stage.

A circuitry for an incremental delta-sigma modulator includes at least an incremental delta-sigma modulator and a sample-and-hold element, the sample-and-hold element being arranged in front of the incremental delta-sigma modulator and providing an input voltage for the incremental delta-sigma modulator in the charged state, wherein the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator, wherein a first switch is arranged in front of the capacitor, and a second switch is arranged behind the capacitor, wherein the first switch is open when the second switch is closed so as to provide, at the incremental delta-sigma modulator, an input voltage decreasing in amount, in particular a decaying input voltage, or wherein the second switch is open when the first switch is closed so as to charge the capacitor of the sample-and-hold element. In addition, a method of operating a circuitry for an incremental delta-sigma modulator is proposed.