An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.

A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate. Each memory cell in the memory cell array includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is configured to establish an electrical connection between the memory cells, and includes a dielectric layer and a plurality of drain conductive structures. At least one drain conductive pillar includes a first contact portion and a second contact portion that are connected to each other and embedded in the dielectric layer. One side surface of the first contact portion is recessed along a first direction with respect to one side surface of the second contact portion, so as to form a stepped structure.

A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

A semiconductor memory device including a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.

An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Technologies relating to crossbar array circuits with parallel ground lines are disclosed. An example crossbar array circuit may include a plurality of transistors. The crossbar array circuit may include an RRAM device connected in series with a first transistor and a second transistor; a first bit line connected to the RRAM device; and a grounding line connected to a body terminal of the first transistor. The grounding line is parallel to the first bit line. In some embodiments, the first transistor is an NMOS transistor. The second transistor is a PMOS transistor

Disclosed herein are core/shell nanoparticles each comprising a metallic core; a shell formed of a metal oxide and surrounding the metallic core; wherein the nanoparticle is characterized by bipolar resistive switching in response to an applied voltage or current. Also disclosed are devices comprising such nanoparticles, as well as methods of using and methods of making such devices.

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

A semiconductor structure and the fabrication method thereof are provided. The semiconductor structure includes: a substrate including a first doped region and a second doped region; a first selection transistor and a second selection transistor located in the substrate; a conductive layer located between the first doped region and the second doped region; a resistive dielectric layer located on sidewalls of the conductive layer, where the conductive layer, the first doped region, and a portion of the resistive dielectric layer facing the first doped region constitute a first variable resistor, and the conductive layer, the second doped region, and a portion of the resistive dielectric layer facing the second doped region constitute a second variable resistor; and an isolation dielectric layer located between the conductive layer and the substrate. The semiconductor structure improves the storage density of resistive random access memory (RRAM).

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.