A process of improving a profile and repairing sidewall damage for phase change memory devices. The process includes applying inert ion beam etching to trim a sidewall of a layer of phase change memory material in a phase change memory device, where the sidewall has been damaged in reactive ion etching using halogens. In the process, the inert ion beam etching is with low energy. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined low temperature. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined small angle between an inert ion beam and a surface tangent of the sidewall.

A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.

A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.

A semiconductor device includes gate electrodes on a substrate, a channel and a resistance pattern. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes in the vertical direction on the substrate. The resistance pattern includes a phase-changeable material. The resistance pattern includes a first vertical extension portion on a sidewall of the channel and extending in the vertical direction, a first protrusion portion on an inner sidewall of the first vertical extension portion and protruding in a horizontal direction substantially parallel to the upper surface of the substrate, and a second protrusion portion on an outer sidewall of the first vertical extension portion and protruding in the horizontal direction and not overlapping the first protrusion portion in the horizontal direction.

A selector device including a first metal electrode layer, a second metal electrode layer and a switching layer disposed between the first metal electrode layer and the second metal electrode layer. The switching layer is a stacked assembly of ABA, BAB, AB or BA, where A is an ion supply layer, and B is a conversion layer. The ion supply layer includes a chalcogenide metal material having a metal atomic content of more than 0% and not more than 50% with respect to the chalcogenide metal material. The conversion layer includes a chalcogenide material.

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

A memory cell and formation thereof. The memory cell including: a first dielectric material having a via; a dielectric spacer on a sidewall of the via, and a second dielectric material pinching off the via and forming a seam.

An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.

A transistor includes a first gate electrode, a first capping layer, a crystalline semiconductor oxide layer, a second capping layer, a first gate dielectric layer, and source/drain contacts. The first capping layer, the crystalline semiconductor oxide layer, and the second capping layer are sequentially disposed over the first gate electrode. Sidewalls of the second capping layer are aligned with sidewalls of the crystalline semiconductor oxide layer. The first gate dielectric layer is located between the first gate electrode and the first capping layer. The source/drain contacts are disposed on the second capping layer. The crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.

Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.