A method for forming a sensor circuit. The method includes forming a plurality of magnetoresistive structures having a first predefined reference magnetization direction in a first common area of a common semiconductor substrate; forming a plurality of magnetoresistive structures having a second predefined reference magnetization direction in a second common area of the common semiconductor substrate; and forming electrically conductive structures electrically coupling the magnetoresistive structures having the first predefined reference magnetization direction to the magnetoresistive structures having the second predefined reference magnetization direction to form a plurality of half-bridge sensor circuits, wherein each half-bridge sensor circuit comprises a magnetoresistive structure having the first predefined reference magnetization direction electrically coupled to a second magnetoresistive structure having the second predefined reference magnetization direction.

A magnetic sensor 1 is provided with: a thin film magnet 20 configured with a hard magnetic material and having magnetic anisotropy in an in-plane direction; a sensitive part 30 including a sensitive element 31 configured with a soft magnetic material and disposed to face the thin film magnet 30, the sensitive element 31 having a longitudinal direction in which a magnetic flux generated by the thin film magnet 20 passes through and a short direction, having uniaxial magnetic anisotropy in a direction crossing the longitudinal direction, and sensing a change in a magnetic field; and a control layer 102 disposed on a side of the thin film magnet 20 opposite to a side of the thin film magnet 20 on which the sensitive element 31 is provided, the control layer 102 controlling the magnetic anisotropy of the thin film magnet 20 to be directed in the in-plane direction.

A computing device including a logic track including two logic-track magnetic domains separated by a logic-track domain wall, an input track arranged crossing the logic track at a first position of the logic track, and an output track arranged crossing the logic track at a second position of the logic track near the logic-track domain wall. The input track includes at least one input-track magnetic domain, and each of the at least one input-track magnetic domain includes at least one input-track storage unit configured to store binary 0 or 1. The output track includes at least one output-track magnetic domain, and each of the at least one output-track magnetic domain includes at least one output-track storage unit configured to store binary 0 or 1.

A magnetic sensor (1) includes: a nonmagnetic substrate (10); and a sensitive element (31) including a plurality of soft magnetic layers (105) (lower soft magnetic layer (105a) and upper soft magnetic layer (105b)) laminated on or above the substrate (10) and a conductor layer (106) laminated between the plurality of soft magnetic layers (105) and having higher conductivity than the plurality of soft magnetic layers (105). The sensitive element (31) has a longitudinal direction and a transverse direction and has uniaxial magnetic anisotropy in a direction intersecting the longitudinal direction. The sensitive element (31) is configured to sense a magnetic field by a magnetic impedance effect.

Provided is a method of a generating a skyrmion. The method includes a step of preparing a magnetic multilayer system and a step of generating a skyrmion at a temperature of 400° C. or higher by adjusting the magnetic anisotropy value and the magnetization value of the magnetic multilayer system.

The present disclosure relates to a composition that includes a nanocrystalline core that includes a perovskite and having an outer surface, and a chiral molecule having a functional group, where the functional group is bonded to a first portion of the outer surface, and the composition is capable of circularly polarized luminescence (CPL). In some embodiments of the present disclosure, the composition is capable of absorbing circularly-polarized light.

A quantum bit array comprises a semiconductor layer, an insulating layer arranged on the semiconductor layer, and a plurality of first gate electrodes which are arranged on the insulating layer. The plurality of first gate electrodes are each configured to trap an electron having a predetermined spin state in the semiconductor layer through application of a voltage. The quantum bit array comprises means for causing, in a case where the spin state of the electron is to be changed, a current for forming a magnetic field that acts on the electron to flow through at least one of the plurality of first gate electrodes in an extending direction of the at least one of the plurality of first gate electrodes.

A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.

A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.

A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.