A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.

A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.

In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

A magnetoresistive device includes a magnetoresistor disposed over a substrate, a stress release structure covering a side surface of the magnetoresistor, an electrical connection structure disposed over the magnetoresistor, and a passivation layer disposed over the electrical connection structure and the stress release structure.

An AND or OR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a AND or OR logic function on applied input magnetization.

A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.

A method of producing a semiconductor substrate comprising at least one integrated magnetic flux concentrator, comprising the steps of: a) providing a semiconductor substrate having an upper surface; b) making at least one cavity in said upper surface; c) depositing one or more layers of one or more materials, including sputtering at least one layer of a soft magnetic material; d) removing substantially all of the soft magnetic material that is situated outside of the at least one cavity, while leaving at least a portion of the soft magnetic material that is inside said at least one cavity. A semiconductor substrate comprising at least one integrated magnetic flux concentrator. A sensor device or a sensor system, a current sensor device or system, a position sensor device or system, a proximity sensor device or system, an integrated transformer device or system.

The present invention provides a selector material, a selector unit and a preparation method thereof and a memory structure, wherein the selector material comprises at least one of Te, Se and S, that is, the selector material is selected from a simple substance such as Te, Se and S or compounds composed of any of these elements, further, the performance can be improved by doping with elements such as O, N, Ga, In, As and the like, or oxides, nitrides and carbides or other dielectric materials. The selector material in the present invention has the advantages of high turn-on current, simple material, fast switching speed, good repeatability and low toxicity when the selector material is used in the selector unit, which is beneficial to achieving high-density three-dimensional information storage.

A magnetic field sensor structure and a method for fabricating the magnetic field sensor structure are disclosed. The magnetic field sensor structure includes at least a magnetoresistive sensor assembly and a transistor assembly, which integrated on a single chip. The transistor assembly includes at least a semiconductor device and a first interconnect. The first interconnect is operably connected to the semiconductor device. The method includes depositing a dielectric layer on the transistor assembly. The method includes removing portions of the dielectric layer to form a first trench that exposes the first interconnect. The method includes performing a damascene process to form an ultra-thick metal (UTM) layer within the first trench to create a first metal coil. The first metal coil is configured as a first reset component. The method includes depositing another dielectric layer on the first metal coil. The method includes forming a flux guide within the another dielectric layer. The method includes forming a second metal coil over the another dielectric layer. The second metal coil is configured as a second reset component. The first reset component and the second reset component are configured as a reset mechanism, which is configured to be responsive to the transistor assembly and operable to magnetize the flux guide to a predetermined orientation.

The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.