A van der Waals capacitor and a qubit constructed with such a capacitor. In some embodiments, the capacitor includes a first conductive layer; an insulating layer, on the first conductive layer; and a second conductive layer on the insulating layer. The first conductive layer may be composed of one or more layers of a first van der Waals material, the insulating layer may be composed of one or more layers of a second van der Waals material, and the second conductive layer may be composed of one or more layers of a third van der Waals material.

A superconducting electronic circuit includes at least two SQUID elements, an array of at least three Josephson Junctions, and a magnetic source element. Each SQUID element has no shared Josephson Junctions or at least one shared Josephson Junction with another SQUID element and at least one exclusive Josephson Junction. The array of at least three Josephson Junctions are connected in one, two, or three-dimensions. The magnetic source element has an electrically-tunable spatially non-uniform magnetic field.

Example implementations include a method of manufacturing a quantum computing device, by depositing a superconducting electrode layer on at least a portion of a superconducting wafer, forming a plurality of electrode pads on the superconducting electrode layer, depositing an electrode bonding interlayer on the electrode pads, singulating the superconducting wafer into a first superconducting die including a first electrode pad among the plurality and a second superconducting die including a second electrode pad among the plurality, and integrating the first superconducting die with the second superconducting die at a bonding interface between the first electrode pad and the second electrode pad.

Example implementations include a method of manufacturing a quantum computing device, by depositing a superconducting electrode layer on at least a portion of a superconducting wafer, forming a plurality of electrode pads on the superconducting electrode layer, depositing an electrode bonding interlayer on the electrode pads, singulating the superconducting wafer into a first superconducting die including a first electrode pad among the plurality and a second superconducting die including a second electrode pad among the plurality, and integrating the first superconducting die with the second superconducting die at a bonding interface between the first electrode pad and the second electrode pad.

A Josephson voltage standard includes: electrical conductors that receive bias currents and radiofrequency biases; a first Josephson junction array that: includes a first Josephson junction and produces a first voltage reference from the first bias current and the third bias current; a second Josephson junction array in electrical communication with the first Josephson junction array and that: includes a second Josephson junction; receives the second bias current; receives the third bias current; receives the second radiofrequency bias; and produces a second voltage reference from the second bias current and the third bias current; a first voltage reference output tap in electrical communication with the first Josephson junction array and that receives the first voltage reference from the first Josephson junction array such that the first voltage reference is electrically available at the first voltage reference output tap; and a second voltage reference output tap.

Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

Qubit circuits having components formed deep in a substrate are described. The qubit circuits can be manufactured using existing integrated-circuit technologies. By forming components such as superconducting current loops, inductive, and/or capacitive components deep in the substrate, the footprint of the qubit circuit integrated within the substrate can be reduced. Additionally, coupling efficiency to and from the qubit can be improved and losses in the qubit circuit may be reduced.

A method for adjusting a resonance frequency of a qubit in a quantum mechanical device includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit comprising capacitor pads; and removing substrate material from the backside of the substrate at an area opposite the at least one qubit to alter a capacitance around the at least one qubit so as to adjust a resonance frequency of the at least one qubit.

Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.