A device is provided. The device includes a first portion having a phase change switch device on a first substrate and a second portion having a semiconductor circuit on a second substrate. The first and second portions are bonded together. A method of manufacturing the device is also described.

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

A phase change switch device (10) is provided comprising a phase change material (11) and a heater device (12) including a transistor thermally coupled to the phase change material. The transistor is configured to have a first electrical resistance in a first state where current is applied to the heater device (12) for heating the phase change material (11), and have a second electrical resistance higher than the first electrical resistance in a second state outside heating phases of the heater device (12).

A phase change switch device (10) is provided comprising a phase change material (11) and a heater device (12) including a transistor thermally coupled to the phase change material. The transistor is configured to have a first electrical resistance in a first state where current is applied to the heater device (12) for heating the phase change material (11), and have a second electrical resistance higher than the first electrical resistance in a second state outside heating phases of the heater device (12).

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

A wafer sensor includes a wafer substrate and a plurality of pixels on the wafer substrate, where each pixel of the plurality of pixels includes a blocking layer, a reflective layer on the blocking layer, a phase change material layer on the reflective layer, and a plurality of metal antennas on the phase change material layer.

A wafer sensor includes a wafer substrate and a plurality of pixels on the wafer substrate, where each pixel of the plurality of pixels includes a blocking layer, a reflective layer on the blocking layer, a phase change material layer on the reflective layer, and a plurality of metal antennas on the phase change material layer.

The present disclosure is directed towards an integrated chip including a heater structure overlying a semiconductor substrate. A phase change element (PCE) is disposed over the heater structure. A thermal barrier structure is disposed between the heater structure and the PCE. Outer sidewalls of the PCE are spaced laterally between outer sidewalls of the thermal barrier structure.

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.