A method of forming a nanoparticle includes forming a layer of semiconductor material on a substrate, forming a first layer on the semiconductor material, and etching the semiconductor layer to form the nanoparticle including the first layer on a first side of the nanoparticle and the semiconductor material on a second side of the nanoparticle.

A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.

A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.

A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.

A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

A silicon capacitor may include a silicon substrate having a three-dimensional pattern, and a dielectric thin film disposed over the silicon substrate and having a structure with a crystal gradient form. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300 C., and embedding crystalline grains in the deposited amorphous thin film by performing plasma treatment. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300 C., and depositing a crystalline layer on the deposited amorphous thin film by performing plasma treatment.

An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

The present disclosure discloses a manufacturing method of a memory device including forming a structure including an epitaxial material plug extending in a vertical direction on a substrate, an epitaxial channel material layer extending in a horizontal direction from a side surface of the epitaxial material plug, and a gate insulating material layer formed on at least a surface portion of the epitaxial channel material layer.

According to one embodiment of the present invention, a method for forming a thin film using a surface protection material comprises: a surface protection layer forming step of forming a surface protection layer on the surface of a substrate by supplying a surface protection material to the inside of a chamber in which the substrate is placed; a step of performing a primary purging of the inside of the chamber; a metal precursor supply step of supplying a metal precursor to the inside of the chamber; a step of performing a secondary purging of the inside of the chamber; and a thin film forming step of supplying a reactive material to the inside of the chamber so as to react with the metal precursor and form a thin film.