Disclosed is an operation method of a memory device which performs a self-refresh operation. The method includes receiving a deep-sleep mode enter command from a memory controller, changing a magnitude of an internal voltage of the memory device from a first voltage to a second voltage smaller than the first voltage, in response to the deep-sleep mode enter command, and entering a self-refresh mode under control of the memory controller, and the internal voltage is maintained at the second voltage during the self-refresh mode.

An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

Methods, systems, and devices for power management techniques are described. A memory system may receive a command to exit a first power mode and enter a second power mode. The first power mode may have a lower power consumption than the second power mode. The memory system may determine whether a duration of an idle period associated with the first power mode satisfies a threshold based on receiving the command to exit the first power mode. The memory system may receive another command associated with executing a flush operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.

Systems and methods for improving power efficiency of electronic systems are disclosed. An intelligent voltage regulator module (VRM) can self-regulate the output power provided to one or more components of an electronic system. For example, output voltage to a component can be increased when more computational power is needed or lowered when appropriate. The intelligent VRM can regulate the output power, for instance, based on one or more of usage or activity of the component. In some cases, the intelligent VRM can independently regulate the output power without input from a host device or override one or more output power parameters. Adjustment of the output power can be performed using machine learning (ML).

A transfer method is performed by an information processing apparatus. The method includes: selecting, based on a load status of the information processing apparatus, candidate transfer data that is among the received data and to be transferred to one or more other information processing apparatuses; selecting, based on load statuses of multiple other information processing apparatuses, one or more candidate transfer destination apparatuses among the multiple other information processing apparatuses as candidate transfer destinations of the data; determining, based on throughput between the information processing apparatus and the candidate transfer destination apparatuses, data to be transferred among the candidate transfer data, transfer destination apparatuses of the data to be transferred among the candidate transfer destination apparatuses, and the sizes of data groups including the data to be transferred; and transferring, to the transfer destination apparatuses determined for the determined data groups, the determined data to be transferred.

Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Adjusting wireless docking resource usage, including identifying, at a client information handling system (IHS), a configuration policy, the client IHS wirelessly connected to a docking station, the docking station providing wireless connections to peripheral computing components, respectively; processing, at the client IHS, the configuration policy, including identifying configuration rules of the configuration policy for performing computer-implemented actions of throttling resource utilization between the client IHS and the docking station; identifying, at the client IHS, when the client IHS is wirelessly connected to the docking station, a first presence state of a user with respect to the client IHS; and determining, at the client IHS, that the first presence state indicates that the user of the client IHS is not actively engaged with the client IHS, and in response, applying the configuration rules to perform computer-implemented actions of throttling resource utilization between the client IHS and the docking station.

A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.