A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

A medical device for use in patient resuscitation and that is configured to communicate with one or more management servers includes a memory, a processor communicably coupled to the memory and configured to store device status information including device-readiness information from a medical device self-test, and store clinical event information observed by the medical device during a use of the medical device during a clinical event, the clinical event information including CPR performance data, and a communication component communicably coupled to the processor and configured to wirelessly transmit the device status information and the clinical event information to the one or more management servers, wherein the medical device includes an external defibrillator, an automated external defibrillator, or a compression assistance device.

Embodiments of the present invention provide a system, a method, and an electronic device for the cloud-based configuration of FPGA configuration data. The system includes a control module internal to an FPGA and a storage module external to the FPGA. The storage module is configured to store configuration data transmitted from a cloud, and the control module is configured to retrieve the configuration data from the storage module and to configure a corresponding processing unit of the FPGA according to the configuration data. In the embodiments of the present invention, the control module internal to the FPGA is provided, and configuration data is retrieved from the storage module external to the FPGA to configure the corresponding processing unit of the FPGA. Accordingly, during FPGA data migration, the configuration data stored in the external storage module can be directly migrated by using a general data migration method, thereby implementing live migration of FPGA data.

The present disclosure relates to systems and methods of device firmware update effects as seen by a computing host. In one example implementation according to aspects of the present disclosure, a method includes executing a first firmware received from a computing host, the first firmware including a first firmware revision identifier, executing a second firmware received from the computing host, and returning the first firmware revision identifier to the computing host during the execution of the second firmware and before an event occurs. The returning the first firmware revision identifier enables the computing host to continue executing without detecting an error in response to a change in a value of a returned firmware revision identifier throughout the execution of the first firmware and during execution of the second firmware.

A processor includes a communicating unit, a receiving unit, a processing unit, and a power-off controller. The receiving unit receives an operation from a user. The processing unit executes processing according to a processing request received by at least one of the communicating unit and the receiving unit. If a power-off request is received from a terminal by the communicating unit, the power-off controller stops the processing unit and disconnects a power supply when the operation received from the user by the receiving unit is not being processed and a condition determined in accordance with a processing mode of the power-off request is satisfied.

Various embodiments are generally directed to techniques for assigning portions of a task among individual cores of one or more processor components of each processing device of a distributed processing system. An apparatus to assign processor component cores to perform task portions includes a processor component; an interface to couple the processor component to a network to receive data that indicates available cores of base and subsystem processor components of processing devices of a distributed processing system, the subsystem processor components made accessible on the network through the base processor components; and a core selection component for execution by the processor component to select cores from among the available cores to execute instances of task portion routines of a task based on a selected balance point between compute time and power consumption needed to execute the instances of the task portion routines. Other embodiments are described and claimed.

Systems and methods for application level authentication are provided for use with the low energy Bluetooth device and accessory. This includes receiving accessory credentials from a server, establishing a Bluetooth low energy connection with the accessory, authenticating with the accessory, and lastly transferring data to the accessory. The transferring of the data may be either a bulk transfer, or a data stream. The authenticating may be an application layer authentication between a device and the accessory using a shared secret key and using a hash function. Additional embodiments include methods for over-the-air firmware updates, and device control of a low energy Bluetooth accessory.

Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes storage drives each comprising a PCIe interface, and configured to store data and retrieve the data stored on associated storage media responsive to data transactions received over a switched PCIe fabric. The data storage system includes processors configured to each manage only an associated subset of the storage drives over the switched PCIe fabric. A first processor is configured to identify first data packets received over a network interface associated with the first processor within a network buffer of the first processor as comprising a storage operation associated with at least one of the plurality of storage drives managed by a second processor, and responsively transfer the first data packets into a network buffer of the second processor.

The disclosure relates to a baseband processing method, comprising: receiving a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section; decoding at least part of the control section to detect a DL grant information; if the DL grant information is detected, determine a number of granted data resource blocks from the DL grant information; and adjust at least one of a clock rate and supply voltage of the baseband processing based on the number of granted resource blocks.

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.