Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

An apparatus includes a plurality of processing cores, and a memory including a plurality of task queues corresponding to the plurality of processing cores, respectively, wherein at least one processing core of the plurality of processing cores is configured, by executing a scheduler, to determine execution of task rescheduling, based on states of the plurality of processing cores, tasks stored in the plurality of task queues, and at least one reference value, and, when the task rescheduling is executed, move a first task stored in a first task queue to a second task queue.

A liquid cooling structure for a server with low-force quickseal joints to carry the coolant includes a first support, a first joint, a second support, a second joint, a first magnet, and a second magnet. The first support is set on the cabinet body. The second support is set on the server body. The first joint is set on the first support. The second joint is arranged on the second support and can be coupled with the first joint. The first magnet is set on first support. The second magnet is set on second support. The first magnet and second magnet with opposite magnetism attract each other to reduce the amount of force required for coupling the first joint and the second joint, and is labor-saving.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Embodiments described herein are generally directed to selective multithreaded execution of memory training by CPU sockets. In an example, a memory configuration and a current phase of execution of memory training for each of multiple CPU sockets of a computer system is received. Based on the memory configuration and the current phase of execution of each of the CPU sockets an estimated power usage across all CPU sockets may be determined. Based on the estimated power usage and a power consumption threshold (e.g., PTAM or PA), performance of the current phase of execution of one or more CPU sockets may be selectively released for one or more channels of the one or more CPU sockets.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.

The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.