Patent classifications
G04F5/00
Real-time clock device and electronic apparatus
A real-time clock device includes a resonator, a clock signal generation circuit, a time-counting circuit, a terminal, and a time-to-digital conversion circuit. The clock signal generation circuit outputs a time-counting clock signal based on an oscillation clock signal. The time-counting circuit generates time-counting data based on the time-counting clock signal. An external signal is input to the terminal. The time-to-digital conversion circuit measures a time difference between a transition timing of a first signal based on the external signal and a transition timing of a second signal based on the oscillation clock signal or the time-counting clock signal with a resolution higher than a time-counting resolution of the time-counting circuit, and obtains time difference information corresponding to the time difference.
Real-time clock device and electronic apparatus
A real-time clock device includes a resonator, a clock signal generation circuit, a time-counting circuit, a terminal, and a time-to-digital conversion circuit. The clock signal generation circuit outputs a time-counting clock signal based on an oscillation clock signal. The time-counting circuit generates time-counting data based on the time-counting clock signal. An external signal is input to the terminal. The time-to-digital conversion circuit measures a time difference between a transition timing of a first signal based on the external signal and a transition timing of a second signal based on the oscillation clock signal or the time-counting clock signal with a resolution higher than a time-counting resolution of the time-counting circuit, and obtains time difference information corresponding to the time difference.
Pulsar based timing synchronization method and system
A pulsar based timing synchronization method and system are disclosed. In one example, a method includes receiving, by a pulsar signal receiver device, a pulse signal emitted from one or more celestial objects and processing, by the pulsar signal receiver device, the pulse signal to discipline a local clock to determine an accurate time output. The method also includes generating, by the pulsar signal receiver device, a timing synchronization signal based on the determined accurate time output. The method further includes providing, by the pulsar signal receiver device, the timing synchronization signal to at least one of a local power system device and a timing distribution network server.
Pulsar based timing synchronization method and system
A pulsar based timing synchronization method and system are disclosed. In one example, a method includes receiving, by a pulsar signal receiver device, a pulse signal emitted from one or more celestial objects and processing, by the pulsar signal receiver device, the pulse signal to discipline a local clock to determine an accurate time output. The method also includes generating, by the pulsar signal receiver device, a timing synchronization signal based on the determined accurate time output. The method further includes providing, by the pulsar signal receiver device, the timing synchronization signal to at least one of a local power system device and a timing distribution network server.
Systems and methods for generating a controllable-width pulse signal
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
Vapor cells with a bidirectional solid-state charge-depletion capacitor for mobile ions
The present invention provides a vapor-cell system comprising: a vapor-cell region configured for vapor-cell optical paths; a first electrode disposed in contact with the vapor-cell region; a second electrode electrically isolated from the first electrode; and an ion conductor interposed between the first electrode and the second electrode. The first electrode, the ion conductor, and the second electrode collectively form a bidirectional solid-state electrochemical charge-depletion capacitor. The ion conductor is ionically conductive for mobile ions, such as Rb.sup.+, Cs.sup.+, Na.sup.+, K.sup.+, or Sr.sup.2+. The first electrode is permeable to the mobile ions and/or neutral atoms formed from the mobile ions. The system can be electrically controlled to quickly pump mobile ions into or out of the vapor-cell region. The system may further contain an atom chip, and the vapor-cell optical paths may be configured to trap a population of cold atoms. Methods of operating these vapor-cell systems are also disclosed.
Real-time clock module, electronic device, and vehicle
A real-time clock module includes a switch circuit that is electrically coupled to a first node to which a first power supply voltage is applied and a second node to which a second power supply voltage is applied and switches between outputting the first power supply voltage and outputting the second power supply voltage, a power supply detection circuit that detects a voltage value of the first power supply voltage, a switch control circuit that controls the switching of the switch circuit based on an output of the power supply detection circuit, a constant voltage circuit that outputs a constant voltage signal based on the output of the switch circuit, and a current control circuit that controls a current supplied to the constant voltage circuit, in which, when where the switch control circuit switches the switch circuit, the current control circuit increases the current supplied to the constant voltage circuit.
Molecular clock with delay compensation
A clock generator includes a hermetically sealed cavity and clock generation circuitry. A dipolar molecule in the hermetically sealed cavity has a quantum rotational state transition at a fixed frequency. The clock generation circuitry generates an output clock signal based on the fixed frequency of the dipolar molecule. The clock generation circuitry includes a detection circuit, a reference oscillator, and control circuitry. The detection circuit generates a first detection signal and a second detection signal representative of amplitude of signal at an output of the hermetically sealed cavity responsive to a first sweep signal and a second sweep signal input to the hermetically sealed cavity. The control circuitry sets a frequency of the reference oscillator based on a difference in time of identification of the fixed frequency of the dipolar molecule in the first detection signal and the second detection signal.
Molecular clock with delay compensation
A clock generator includes a hermetically sealed cavity and clock generation circuitry. A dipolar molecule in the hermetically sealed cavity has a quantum rotational state transition at a fixed frequency. The clock generation circuitry generates an output clock signal based on the fixed frequency of the dipolar molecule. The clock generation circuitry includes a detection circuit, a reference oscillator, and control circuitry. The detection circuit generates a first detection signal and a second detection signal representative of amplitude of signal at an output of the hermetically sealed cavity responsive to a first sweep signal and a second sweep signal input to the hermetically sealed cavity. The control circuitry sets a frequency of the reference oscillator based on a difference in time of identification of the fixed frequency of the dipolar molecule in the first detection signal and the second detection signal.
Systems and methods for generating a controllable-width pulse signal
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.