Patent classifications
H01G2/00
Fork structure for positive retention and centering a wire for electrical connection
An electronic device includes a fork structure having a pair of arms disposed in spaced relation and defining an open-ended channel therebetween. A surface of channel defines a seat opposite the open end. The channel has a width W.sub.1 at its narrowest section. A rigid wire of an electrical component is disposed in the channel generally adjacent to the seat. The wire has a width W.sub.2 that is greater than the width W.sub.1 so surfaces of the channel at the narrowest section defined by width W.sub.1 interfere with the wire, preventing the wire from moving towards the open end of the channel. The pair of arms are constructed and arranged to be moved toward each other so as to crimp the wire to the fork structure.
Fork structure for positive retention and centering a wire for electrical connection
An electronic device includes a fork structure having a pair of arms disposed in spaced relation and defining an open-ended channel therebetween. A surface of channel defines a seat opposite the open end. The channel has a width W.sub.1 at its narrowest section. A rigid wire of an electrical component is disposed in the channel generally adjacent to the seat. The wire has a width W.sub.2 that is greater than the width W.sub.1 so surfaces of the channel at the narrowest section defined by width W.sub.1 interfere with the wire, preventing the wire from moving towards the open end of the channel. The pair of arms are constructed and arranged to be moved toward each other so as to crimp the wire to the fork structure.
Multilayer capacitor and board having the same mounted thereon
A multilayer capacitor includes a capacitor body including an active region having dielectric layers and internal electrodes alternately stacked therein, the capacitor body including upper and lower covers disposed on upper and lower surfaces of the active region, respectively; and an external electrode disposed on an external surface of the capacitor body. In one of the upper and lower covers, a portion thereof between a boundary surface of the active region and a boundary surface of the capacitor body is divided into a first cover region adjacent to the active region and a second cover region adjacent to the boundary surface of the capacitor body, and the first cover region includes grains having a core-shell structure doped with Sn. The first cover region includes 20% or more of Sn-doped core-shell structure grains, compared to the total of grains in the first cover region.
Multilayer capacitor and board having the same mounted thereon
A multilayer capacitor includes a capacitor body including an active region having dielectric layers and internal electrodes alternately stacked therein, the capacitor body including upper and lower covers disposed on upper and lower surfaces of the active region, respectively; and an external electrode disposed on an external surface of the capacitor body. In one of the upper and lower covers, a portion thereof between a boundary surface of the active region and a boundary surface of the capacitor body is divided into a first cover region adjacent to the active region and a second cover region adjacent to the boundary surface of the capacitor body, and the first cover region includes grains having a core-shell structure doped with Sn. The first cover region includes 20% or more of Sn-doped core-shell structure grains, compared to the total of grains in the first cover region.
SWITCH AND METHOD FOR FABRICATING THE SAME, AND RESISTIVE MEMORY CELL AND ELECTRONIC DEVICE, INCLUDING THE SAME
A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
Battery state of charge indicator with an indicator circuit
A state of charge indicator including an indicator with a display threshold and an indicator circuit electrically coupled to the indicator such that when a main cell voltage of a main cell is greater than a display threshold, the indicator circuit applies a driver voltage to the indicator such that the indicator is inactive and when the main cell voltage is less than the display threshold, the indicator circuit applies the driver voltage to the indicator such that the indicator is active.
Battery state of charge indicator with an indicator circuit
A state of charge indicator including an indicator with a display threshold and an indicator circuit electrically coupled to the indicator such that when a main cell voltage of a main cell is greater than a display threshold, the indicator circuit applies a driver voltage to the indicator such that the indicator is inactive and when the main cell voltage is less than the display threshold, the indicator circuit applies the driver voltage to the indicator such that the indicator is active.
Gas sensor
A gas sensor includes: a substrate; a first conductor and a second conductor that are disposed on the substrate; an insulating layer; and an adsorbent layer. The insulating layer covers the first conductor and the second conductor, and has a first opening that allows a part of a surface of the first conductor to be exposed therethrough and a second opening that allows a part of a surface of the second conductor to be exposed therethrough. The adsorbent layer contains a conductive material and an organic adsorbent that can adsorb a gas. The adsorbent layer is in contact with the first conductor and the second conductor respectively through the first opening and the second opening.
3D ultrasound imaging system
A circuit for 3D ultrasound imaging systems includes multiple sensor units, multiple unit circuits and multiple row sharing circuits. The unit circuits are connected with the sensor units respectively. Each row of unit circuits share a row sharing circuit. Each unit circuit includes a first electrically controlled switch, a second electrically controlled switch and a control circuit. Each row sharing circuit includes a signal transmission bus, a signal receiving bus and a row main control circuit. The signal transmission bus and the signal receiving bus of each row sharing circuit extend through a corresponding row of unit circuits. The row main control circuit of each row is configured to transmit main control signals, transmission control signals and receiving control signals to a corresponding row of unit circuits so as to select the corresponding sensor units to transmit or receive ultrasound signals.
3D ultrasound imaging system
A circuit for 3D ultrasound imaging systems includes multiple sensor units, multiple unit circuits and multiple row sharing circuits. The unit circuits are connected with the sensor units respectively. Each row of unit circuits share a row sharing circuit. Each unit circuit includes a first electrically controlled switch, a second electrically controlled switch and a control circuit. Each row sharing circuit includes a signal transmission bus, a signal receiving bus and a row main control circuit. The signal transmission bus and the signal receiving bus of each row sharing circuit extend through a corresponding row of unit circuits. The row main control circuit of each row is configured to transmit main control signals, transmission control signals and receiving control signals to a corresponding row of unit circuits so as to select the corresponding sensor units to transmit or receive ultrasound signals.