A method for attaching two electronics boards, e.g., a testing PCB and a space transformer, comprises rack welding resin prepreg and a mylar film to a testing PCB; laser drilling via holes in the resin prepreg and mylar film such that the holes are aligned on one side of the resin prepreg with connection/capture pads on the testing PCB and aligned (after attachment) on the other side of the resin prepreg with connection capture pads on a space transformer, filling the via holes with sintering paste; applying a pressure treatment to remove air, bubbles, and voids from the sintering paste; removing the mylar film; and using a lamination press cycle to attach a space transformer to the resin prepreg.

A PCB that constructs circuit traces, vias, and connection pads by filling recessed areas, grooves, holes, and/or counter bores with conductive material. The recessed areas are filled with conductive ink or plating solutions by a number of methods. Capillary action aids in the filling of the recessed areas. Pressure, vacuum and or gravity can aid the filling. Layers of the PCB or similar type devices can be bonded together both mechanically and electrically to accomplish 3D connections of circuits. Ground and power plane durability and conductivity is enhanced by the inclusion of small grooves over the conductive plane.

A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.

A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. The at least one electrically conductive layer structure includes a first trace. A tapering trench is formed in the at least one electrically insulating layer structure beside and below the first trace. A method of manufacturing the component carrier is also described.

A conductor non-formed portion where no conductor layer exists is provided in a first ground conductor layer. A multilayer body is provided with a void where no insulating resin exists. At least a portion of the conductor non-formed portion is provided in a first area positioned at a right of a first interlayer connection conductor with respect to a multilayer body left-right direction and at left of a second interlayer connection conductor with respect to the multilayer body left-right direction in a view in a multilayer body downward direction. At least a portion of a void overlaps with the conductor non-formed portion in the view in the multilayer body downward direction and is provided above a first signal conductor layer with respect to a multilayer body up-down direction and below the first ground conductor layer with respect to the multilayer body up-down direction.

A method of manufacturing a component carrier includes forming a poorly adhesive structure on at least one layer structure, thereafter removing part of the poorly adhesive structure to thereby define a lateral limit of the poorly adhesive structure, thereafter attaching at least one further layer structure to the at least one layer structure and to the poorly adhesive structure, and forming a cavity by removing material of the at least one further layer structure above the poorly adhesive structure.

A printed circuit board may include a substrate body portion, conductive patterns on a top surface of the substrate body portion, and a photosensitive insulating layer on the top surface of the substrate body portion and including an opening exposing at least one of the conductive patterns. The photosensitive insulating layer includes first to third sub-layers stacked sequentially. The first sub-layer includes an amine compound or an amide compound A refractive index of the second sub-layer is lower than a refractive index of the third sub-layer. A photosensitizer content of the second sub-layer is higher than a photosensitizer content of the third sub-layer.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure. The stack has at least one central stack section, at least one cavity stack section, and at least one vertical opening formed in the cavity stack section. The cavity stack section at least partially surrounds the central stack section, and the thickness of the central stack section is greater than the thickness of the cavity stack section.

An electronic assembly including a thermal capacitor. An electronic substrate of the electronic assembly includes one or more insulating layers and one or more conductor layers provided along the one or more insulating layers. The one or more conductor layers including a conductive material. A shape memory thermal capacitor is received in the electronic substrate. The shape memory thermal capacitor includes a shape memory core including a shape memory material.

An electronic assembly including a thermal capacitor. An electronic substrate of the electronic assembly includes one or more insulating layers and one or more conductor layers provided along the one or more insulating layers. The one or more conductor layers including a conductive material. A shape memory thermal capacitor is received in the electronic substrate. The shape memory thermal capacitor includes a shape memory core including a shape memory material.