A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A mask read only memory device is provided. Single-transistor memory cells are arranged in rows and columns. Each word line is associated with a corresponding row. Each bit line is associated with a corresponding column. Each first reference line selectively provides a first potential in a first phase and a second potential in a second phase. Each second reference line selectively provides the second potential in the first read phase and the first potential in the second phase. Each memory cell has a gate coupled to a word line, a drain coupled to a bit line and a source terminal either floating, grounded or coupled to one among a first reference line and a second reference line. One of first to fourth logic values is read during the memory cell.

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first doped region; a first isolation structure located in the first doped region, a depth of the first isolation structure being greater than that of the first doped region; a first gate structure located on the surface of the substrate of the first doped region and spanning the first isolation structure, a projection width of the first gate structure on the substrate being larger than that of the first isolation structure on the substrate; and second gate structures located on the surface of the substrate and at both sides of the first gate structure.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising: exposing a pattern on a wafer for creating structures for a plurality of memory cells for the semiconductor memory device, wherein the pattern is exposed by means of one or more charged particle beams; and varying an exposure dose of the one or more charged particle beams during exposure of the pattern to generate a set of one or more non-common features in one or more structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device.

A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising; exposing a pattern on a wafer for creating structures for a plurality of memory cells for the semiconductor memory device, wherein the pattern is exposed by means of one or more charged particle beams; and varying an exposure dose of the one or more charged particle beams during exposure of the pattern to generate a set of one or more non-common features in one or more structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.