A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.

The present disclosure provides a method for improving an FDSOI device leakage, including steps of: defining a bulk silicon region on the semiconductor structure, and forming an recess area by removing a silicon nitride layer, a first oxide layer, an SOI layer, and a buried oxide layer in the bulk silicon region by etch, wherein the etch is stopped at the silicon substrate; refilling the recess area in the bulk silicon region with monocrystalline silicon, until the monocrystalline silicon reaches a same height as that of the SOI layer outside of the bulk silicon region; forming an STI region, and performing ion implantation on the bulk silicon region; and forming a device structure in the bulk silicon region. In the present disclosure, a doping condition for the bulk silicon region is selected to meet the demands of the device, thereby solving the problem of the device leakage.

A semiconductor structure includes a semiconductor substrate, a semiconductor island, a shallow trench isolation (STI) region, a first buried layer, and a second buried layer. The semiconductor substrate has an original surface. The semiconductor island is formed based on the semiconductor substrate. The shallow trench isolation (STI) region surrounds the semiconductor island. The first buried layer is a localized layer under the semiconductor island, wherein a material of the first buried layer is different from that of the semiconductor substrate. The second buried layer is a localized layer under the first buried layer, wherein a material of the second buried layer is different from that of the semiconductor substrate.

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

A display device with high display quality is provided. A display device with low power consumption is provided. In the display device, a first transistor, a second transistor, a first conductive layer, and a light-emitting diode package are included in a pixel. The light-emitting diode package includes a first light-emitting diode, a second light-emitting diode, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first light-emitting diode includes a first electrode and a second electrode. The second light-emitting diode includes a third electrode and a fourth electrode. One of a source and a drain of the first transistor is electrically connected to the first electrode through the second conductive layer.

10 One of a source and a drain of the second transistor is electrically connected to the third electrode through the third conductive layer. The first conductive layer is electrically connected to each of the second electrode and the fourth electrode through the fourth conductive layer. A constant potential is supplied to the first conductive layer.

Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

A microelectronic structure including a logic device and a passive device. The passive device includes a doped substrate, a silicide layer located on a backside surface of the doped substrate, and a metal plane located on a backside surface of the silicide layer.

A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.