A method for manufacturing a capacitor array includes: providing a substrate provided with a device area configured for forming a capacitor and a peripheral area located at a periphery of the device area; forming successively a first support layer and a first sacrificial layer on the substrate; etching the first sacrificial layer of the peripheral area to expose the first support layer, so as to form a first via; and filling the first via to form a support pillar.

There is provided a high dielectric film including amorphous hydrocarbon of which a dielectric constant is 10 or more. A leakage current of the high dielectric film is 1 A/cm.sup.2 or less, and an insulation level is 1 MV/cm or more. Rms surface roughness of the high dielectric film is 20 nm or less.

A method according to an embodiment is for forming a capacitor structure on a wafer. A first capacitor is formed on a first side of a wafer, and a second capacitor is formed on a second side of the wafer. The capacitor structure includes the first capacitor and the second capacitor. A trench capacitor is fabricated at both ends of an interposer, which can increase capacitance, and greatly improve the stability of the supplied power.

A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.

According to one embodiment of the present invention, a method for forming a thin film using a surface protection material comprises: a surface protection layer forming step of forming a surface protection layer on the surface of a substrate by supplying a surface protection material to the inside of a chamber in which the substrate is placed; a step of performing a primary purging of the inside of the chamber; a metal precursor supply step of supplying a metal precursor to the inside of the chamber; a step of performing a secondary purging of the inside of the chamber; and a thin film forming step of supplying a reactive material to the inside of the chamber so as to react with the metal precursor and form a thin film.

The present disclosure provides a substrate integrated with a passive device and a method for manufacturing the same, and belongs to the technical field of communications. The substrate integrated with a passive device according to the present disclosure includes a dielectric layer provided with a first connection via; and the passive device at least including an inductor. The inductor includes a plurality of first sub-structures and a plurality of second sub-structures respectively disposed on two opposite sides of the dielectric layer, and two adjacent first sub-structures of the plurality of first sub-structures are short-circuited by a corresponding one of the plurality of second sub-structures through the first connection via penetrating through the dielectric layer, so as to form an induction coil of the inductor.

A preparation method of a capacitor array structure includes: providing a capacitor substrate which comprises an upper electrode filling layer; forming an insulating layer on a side face of the upper electrode filling layer; forming an upper electrode metal layer on an upper surface of the upper electrode filling layer; forming a planarization layer on an outer surface of the upper electrode metal layer; and forming a first conductor which is connected to the upper electrode metal layer after running through the planarization layer as well as a second conductor which is connected to a lower circuit after running through the planarization layer, the insulating layer and an isolation layer.

The present disclosure provides a method of forming a semiconductor structure and a semiconductor structure. The method of forming the semiconductor structure includes: providing an initial structure, where the initial structure includes a substrate and a dielectric layer; forming a conductive trench, where a distance between a bottom surface of the conductive trench and a second side surface of the substrate is a first spacing; forming a conductive hole, where the conductive hole extends to the second side surface of the substrate from a top surface of the dielectric layer; forming a conductive pillar, where the conductive pillar fills the conductive hole; forming an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

A silicon capacitor may include a silicon substrate having a three-dimensional pattern, and a dielectric thin film disposed over the silicon substrate and having a structure with a crystal gradient form. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and embedding crystalline grains in the deposited amorphous thin film by performing plasma treatment. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and depositing a crystalline layer on the deposited amorphous thin film by performing plasma treatment.