A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

A semiconductor wafer transport apparatus includes a frame, a transport arm movably mounted to the frame and having at least one end effector movably mounted to the arm so the at least one end effector traverses, with the arm as a unit, in a first direction relative to the frame, and traverses linearly, relative to the transport arm, in a second direction, and an edge detection sensor mounted to the transport arm so the edge detection sensor moves with the transport arm as a unit relative to the frame, the edge detection sensor being a common sensor effecting edge detection of each wafer simultaneously supported by the end effector, wherein the edge detection sensor is configured so the edge detection of each wafer is effected by and coincident with the traverse in the second direction of each end effector on the transport arm.

A semiconductor device includes: a substrate including a main chip area and a scribe lane area, wherein chip circuits are disposed in the main chip area, and the scribe lane area surrounds the main chip area; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer and in which a plurality of guard rings are embedded; a dielectric layer disposed on the second insulating layer; and a third insulating layer disposed on the dielectric layer, wherein the scribe lane area includes a first area and a second area, wherein the first area is adjacent to the main chip area based on a decreasing point of a thickness of the third insulating layer, wherein the plurality of guard rings includes a first guard ring disposed in the first area and a second guard ring disposed in the second area.

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

A semiconductor structure including a first structure of a first wafer including a first substrate layer, a first device layer disposed on the first substrate layer, a first bonding layer disposed on the first device layer including a first portion of an alignment mark, and a second structure of a second wafer including a second substrate layer, a second device layer disposed on the second substate layer, a second bonding layer disposed on the second device layer including a second portion of the alignment mark, wherein the first portion of the alignment mark and the second portion of the alignment mark forms the alignment mark configured to provide an alignment for bonding cross the first bonding layer and the second bonding layer. The first device layer or the second device layer may include a three-dimensional NAND flash memory circuit as a part of a storage media with high-performance and high-capacity.

Provided are an SiC-semiconductor device (1) having properties capable of maximizing the device strength when cut from an SiC-semiconductor wafer (11) by SnB, and a method of manufacturing the SiC-semiconductor device.

The SiC-semiconductor device is produced by, after forming scribe lines (L) in the wafer (11) with a scribing tool, dividing the wafer with external-force application along the lines (L). Created in a sidewall surface of the device (1) is a longitudinal stripe (TL) extending continuously to C surface from a predetermined depth in the sidewall surface exclusive of plastically-deformable region of Si surface and vertical-cracking region formed immediately below the plastically deformable region. The stripe (TL) fulfills the condition of being rectilinearly-shaped or the condition where exterior angle formed by intersection of a longitudinal stripe (TL) extending upward from the C (lower) surface with a deflected stripe (KL) resulting from first-time deflection of the stripe (TL) falls within 10.

Embodiments disclosed herein include semiconductor devices. In an embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment a fiducial is on the substrate. In an embodiment, the fiducial is a cantilever beam that extends out past an edge of the substrate.

The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.

The disclosure provides a method of manufacturing an electronic device. The method of manufacturing the electronic device includes the following steps: providing a transparent carrier having an accommodation space, wherein the transparent carrier has a first mark; disposing a sample in the accommodation space of the transparent carrier, wherein the sample has a second mark; calculating an offset of the sample according to the first mark, the second mark, and a standard value; and forming a third mark on the sample or the transparent carrier according to the offset. The method of manufacturing of the electronic device of the disclosure may improve process yield or reliability.

Various systems and methods for imprinting a unique identifier on a semiconductor die are disclosed herein. Example embodiments involve receiving a substrate at a photolithography station, the substrate including a photosensitive layer and an area for forming semiconductor dies, forming circuits on the substrate using a photolithography mask, imprinting a unique identifier on each semiconductor die on the substrate using a digital photomask and removing the substrate containing the semiconductor dies containing the circuits and the unique identifiers from the photolithography station. In some embodiments, each unique identifier is associated with a unique record for recording characteristics of the substrate, of the semiconductor die and of the unique identifier. In some embodiments, the digital photomask includes dynamically-controlled pixels, controllable to define a unique pattern for each unique identifier. In some embodiments, the unique identifier is a two-dimensional code.