An electrolytic processing jig configured to perform an electrolytic processing on a processing target substrate includes a base body having a flat plate shape; an electrode provided at the base body; three or more terminals provided at the base body, each having elasticity and configured to be brought into contact with a peripheral portion of the processing target substrate; and a detecting unit configured to electrically detect a contact of at least one of the terminals with the processing target substrate.

A plating method for plating a substrate by increasing a current value from a predetermined current value to a first current value is provided. The plating method plates the substrate for a first predetermined period with the first current value when a first current density corresponding to the first current value is lower than a limiting current density. This plating method includes measuring a voltage value applied to the substrate, and when the current value is increased from the predetermined current value to the first current value, determining whether the first current density is equal to or more than the limiting current density or not based on an amount of change in the voltage value.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.

Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrode-position of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

Provided is a technique that allows ensuring a downsized plating apparatus.

A plating apparatus includes a discharge module 50. The discharge module includes a module main body 51 including a plurality of nozzles 52 configured to discharge a process liquid upward, and a moving mechanism 60 including a rotation shaft 61 disposed at a side of a plating tank and connected to the module main body. The moving mechanism 60 moves the module main body by rotation of the rotation shaft. The moving mechanism moves the module main body between the first position and the second position. The plurality of nozzles are arranged such that the process liquid discharged from the plurality of nozzles is brought in contact with a lower surface of a substrate from a center portion to an outer peripheral edge portion when the module main body moves to the second position. The module main body further includes a recovery member configured to recover the process liquid dropped after being discharged from the plurality of nozzles and brought in contact with the lower surface of the substrate.

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

A method of forming an electrode in accordance with an exemplary embodiment includes a process of forming a mask pattern on one surface of a base to expose a partial area of the one surface of the base by using a mask material that is polymer including an end tail having at least one bonding structure of covalent bond and double bond, a process of loading the base on which the mask pattern is formed into a chamber, and a process of forming a conductive layer containing copper on the exposed one surface of the base by using an atomic layer deposition method that alternately injects a source material containing copper and a reactive material that reacts with the source material into the chamber.

Thus, according to the method of forming an electrode in accordance with an exemplary embodiment, a thin-film caused by a material for forming an electrode is not formed on a surface of the mask pattern. Therefore, a residue is not remained when the mask pattern is removed to prevent a defect caused by the residue from being generated.

Disclosed are cup assemblies for holding, sealing, and providing electrical power to a semiconductor substrate during electroplating which may include a cup bottom element having a main body portion and a moment arm, an elastomeric sealing element disposed on the moment arm, and an electrical contact element disposed on the elastomeric sealing element. The main body portion may be such that it does not substantially flex when a substrate is pressed against the moment arm, and it may be rigidly affixed to another feature of the cup structure. The ratio of the average vertical thickness of the main body portion to that of the moment arm may be greater than about 5. The electrical contact element may have a substantially flat but flexible contact portion disposed upon a substantially horizontal portion of the sealing element. The elastomeric sealing element may be integrated with the cup bottom element during manufacturing.