Patent classifications
C25D7/123
ELECTROCHEMICAL ADDITIVE MANUFACTURING METHOD USING DEPOSITION FEEDBACK CONTROL
A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.
Composition for cobalt or cobalt alloy electroplating
A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.
Zinc-cobalt barrier for interface in solder bond applications
A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.
Cross flow conduit for foaming prevention in high convection plating cells
The embodiments herein relate to apparatuses and methods for electroplating one or more materials onto a substrate. Embodiments herein utilize a cross flow conduit in the electroplating cell to divert flow of fluid from a region between a substrate and a channeled ionically resistive plate positioned near the substrate down to a level lower than level of fluid in a fluid containment unit for collecting overflow fluid from the plating system for recirculation. The cross flow conduit can include channels cut into components of the plating cell to allow diverted flow, or can include an attachable diversion device mountable to an existing plating cell to divert flow downwards to the fluid containment unit. Embodiments also include a flow restrictor which may be a plate or a pressure relief valve for modulating flow of fluid in the cross flow conduit during plating.
Plating apparatus for plating semiconductor wafer and plating method
A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.
Apparatus and method for wafer pre-wetting
A semiconductor apparatus and methods of processing a semiconductor workpiece are provided. The semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece comprising a plurality of recess portions.
HIGH-SPEED 3D METAL PRINTING OF SEMICONDUCTOR METAL INTERCONNECTS
A system for printing metal interconnects on a substrate includes an anode substrate. A plurality of anodes are arranged on one side of the anode substrate with a first predetermined gap between adjacent ones of the plurality of anodes. A first plurality of fluid holes have one end located between the plurality of anodes. A plurality of control devices is configured to selectively supply current to the plurality of anodes, respectively. The anode substrate is arranged within a second predetermined gap of a work piece substrate including a metal seed layer. A ratio of the second predetermined gap to the first predetermined gap is in a range from 0.5:1 and 1.5:1. An array controller is configured to energize selected ones of the plurality of anodes using corresponding ones of the plurality of control devices while electrolyte solution is supplied through the first plurality of fluid holes between the anode substrate and the work piece substrate.
METHOD OF COUPLING SEMICONDUCTOR DICE, TOOL FOR USE THEREIN AND CORRESPONDING SEMICONDUCTOR DEVICE
An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.
Composition for metal electroplating comprising leveling agent
A method of detecting space debris includes: generating a virtual space debris in accordance with the law of conservation of mass by applying a debris breakup model to an object of breakup origin; calculating an orbit of each virtual space debris based on a debris orbit propagation model; and generating appearance frequency distribution of a motion vector of each virtual space debris on the celestial sphere based on the orbit calculation. The above operations are executed multiple times. The method further includes setting a search range vector based on a motion vector having a high level of the appearance frequency distribution of the motion vector, and applying a stacking method to regions in images captured at time intervals during the fixed point observation, the regions being shifted along the search range vector sequentially in the order of capture, thereby detecting space debris appearing on the images.
Semiconductor dies having ultra-thin wafer backmetal systems, microelectronic devices containing the same, and associated fabrication methods
Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.