A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

A calibration system adapted to calibrate a resistance of an electrical device having a lead wire comprises a resistance detector adapted to detect the resistance of the electrical device, a first container containing an etching solution adapted to etch the lead wire, and a heater configured to heat the electrical device. If a first resistance of the electrical device detected by the resistance detector at a first temperature is within a first predetermined range, the electrical device is heated with the heater to a second temperature higher than the first temperature. A second resistance of the electrical device is detected by the resistance detector at the second temperature. If the second resistance is beyond a second predetermined range, the lead wire is etched by the etching solution to adjust the resistance of the electrical device until the second resistance at the second temperature is within the second predetermined range.

A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.

A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.

An adaptive protection method for impedance of parallel capacitors comprises monitoring a terminal voltage and current of the capacitor; automatically calibrating the initial impedance of the capacitor when the capacitor is put into operation; calculating a real-time impedance of the capacitor during operation, dynamically updating the actual impedance of the capacitor periodically; comparing the real-time impedance of the capacitor with the actual impedance, updating the actual impedance if the relative value of the modulus of the real-time impedance change does not exceed the dynamic update limit threshold and the dynamic update reaches update period; generating an update failure alarm if the relative value of the modulus of the real-time impedance change exceeds the dynamic update limit threshold; generating a protection alarm if the relative value of the modulus of the real-time impedance change satisfies the protection alarm condition and the delay time is reached; and protecting the trip outlet if the relative value of the modulus of the real-time impedance change satisfies the protection trip condition and the delay time is reached. The protection method is applicable to various fault conditions of the capacitor and the capacitor bank, the set value is simple to calculate, the implementation is simple, and the sensitivity and reliability of the protection for capacitor are effectively improved.

An apparatus, a method and a computer program product for defect detection in work pieces is disclosed. At least one light source is provided and the light source generates an illumination light of a wavelength range at which the work piece is transparent. A camera images the light from at least one face of the work piece on a detector of the camera by means of a lens. A stage is used for moving the work piece and for imaging the at least one face of the semiconductor device completely with the camera. The computer program product is disposed on a non-transitory, computer readable medium for defect detection in work pieces. A computer is used to execute the various process steps and to control the various means of the apparatus.

An apparatus, a method and a computer program product for defect detection in work pieces is disclosed. At least one light source is provided and the light source generates an illumination light of a wavelength range at which the work piece is transparent. A camera images the light from at least one face of the work piece on a detector of the camera by means of a lens. A stage is used for moving the work piece and for imaging the at least one face of the semiconductor device completely with the camera. The computer program product is disposed on a non-transitory, computer readable medium for defect detection in work pieces. A computer is used to execute the various process steps and to control the various means of the apparatus.

In a described example, a device includes: a probe card with a tester side surface and a device side surface opposite the tester side surface; a probe insert having a first surface that is removably affixed to the device side surface of the probe card; and at least one or more probes extending from a second surface of the probe insert that is opposite the first surface of the probe insert.

In a described example, a device includes: a probe card with a tester side surface and a device side surface opposite the tester side surface; a probe insert having a first surface that is removably affixed to the device side surface of the probe card; and at least one or more probes extending from a second surface of the probe insert that is opposite the first surface of the probe insert.