G06F7/76

MIXED-SIGNAL ACCELERATION OF DEEP NEURAL NETWORKS
20220350662 · 2022-11-03 ·

Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation. The apparatus also includes an analog-to-digital converter coupled to the circuitry to convert the analog-domain result into a digital-domain result.

MIXED-SIGNAL ACCELERATION OF DEEP NEURAL NETWORKS
20220350662 · 2022-11-03 ·

Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation. The apparatus also includes an analog-to-digital converter coupled to the circuitry to convert the analog-domain result into a digital-domain result.

COMPUTING DEVICE AND METHOD

A computing device and an operation method thereof are disclosed. The method includes unshuffling first image data to generate input data, generating output data by implementing a neural network (NN) model provided the input data, and generating second image data by shuffling the output data.

COMPUTING DEVICE AND METHOD

A computing device and an operation method thereof are disclosed. The method includes unshuffling first image data to generate input data, generating output data by implementing a neural network (NN) model provided the input data, and generating second image data by shuffling the output data.

Secret table reference system, method, secret calculation apparatus and program

A secure table reference system includes a first combining part 11.sub.n for generating [v′] of v′ ∈ F.sup.m+nt in which d and v are combined, a difference calculation part 12.sub.n for generating [r″] of r″ that has a difference between a certain element of r and an element before the certain element as an element corresponding to the certain element, a second combining part 13.sub.n for generating [r′] of r′ ∈ F.sup.m+nt in which r″ and an m-dimensional zero are combined, a permutation calculation part 14.sub.n for generating {{σ}} of a permutation σ that stably sorts v′ in ascending order, a permutation application part 15.sub.n for generating [s] of s: =σ(r′) obtained by applying the permutation σ to r′, a vector generation part 16.sub.n for generating [s′] of a prefix-sum s′ of s, an inverse permutation application part for generating [s″] of s″ obtained by applying an inverse permutation σ.sup.−1 of the permutation σ to s′, and an output part 17.sub.n for generating [x] of x ∈ F.sup.m consisting of (n.sub.t+1)th and subsequent elements of s″.

Secret table reference system, method, secret calculation apparatus and program

A secure table reference system includes a first combining part 11.sub.n for generating [v′] of v′ ∈ F.sup.m+nt in which d and v are combined, a difference calculation part 12.sub.n for generating [r″] of r″ that has a difference between a certain element of r and an element before the certain element as an element corresponding to the certain element, a second combining part 13.sub.n for generating [r′] of r′ ∈ F.sup.m+nt in which r″ and an m-dimensional zero are combined, a permutation calculation part 14.sub.n for generating {{σ}} of a permutation σ that stably sorts v′ in ascending order, a permutation application part 15.sub.n for generating [s] of s: =σ(r′) obtained by applying the permutation σ to r′, a vector generation part 16.sub.n for generating [s′] of a prefix-sum s′ of s, an inverse permutation application part for generating [s″] of s″ obtained by applying an inverse permutation σ.sup.−1 of the permutation σ to s′, and an output part 17.sub.n for generating [x] of x ∈ F.sup.m consisting of (n.sub.t+1)th and subsequent elements of s″.

IMPORTANCE CALCULATION APPARATUS, METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

According to one embodiment, an importance calculation apparatus includes a processing circuit. The processing circuit obtains data in which samples each including values regarding a plurality of explanatory variables and one response variable are arranged in a predetermined order. The processing circuit generates first data in which a first correspondence between the values of the plurality of explanatory variables and the values of the response variable is randomized between the samples in the data, and second data in which a correspondence between the values of at least one target explanatory variable among the plurality of explanatory variables and the values of the response variable is restored to the first correspondence in the first data.

IMPORTANCE CALCULATION APPARATUS, METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

According to one embodiment, an importance calculation apparatus includes a processing circuit. The processing circuit obtains data in which samples each including values regarding a plurality of explanatory variables and one response variable are arranged in a predetermined order. The processing circuit generates first data in which a first correspondence between the values of the plurality of explanatory variables and the values of the response variable is randomized between the samples in the data, and second data in which a correspondence between the values of at least one target explanatory variable among the plurality of explanatory variables and the values of the response variable is restored to the first correspondence in the first data.

Managing devices within a vehicular communication network

A system for determining the servicing needs of a vehicle. In various embodiments, the system includes a remote server and a vehicle control module of the vehicle. The vehicle control module includes a first communication interface to enable communications with at least one vehicle device via a network fabric of the vehicle. The vehicle control module is configured to receive status data, from the vehicle device, relating to a performance status or operational status of the vehicle. The vehicle control module further includes a second communication interface that enables wireless communications with the remote server. The wireless communications include sending status data to the remote server. The remote server is configured to receive and interpret the status data to determine if the vehicle requires service, and send a response to the vehicle. When service is required, the response may cause the vehicle to provide a service indication.

MASKED SHIFTED ADD OPERATION
20230075534 · 2023-03-09 ·

A computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift add operation with a set of operands. A logical AND operation is performed on a first pair of operands from the set of operands to obtain a first intermediate result. The first intermediate result is shifted by a first shift amount that is based on a first operand from the first pair of operands. A logical AND operation is performed on a second pair of operands from the set of operands to obtain a second intermediate result. The second intermediate result is shifted by a second shift amount that is based on a first operand from the second pair of operands. The shifted first intermediate result is added with the shifted second intermediate result. The method further includes outputting, as a result of the masked shift add operation, an output of the adding.