Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

Provided is a semiconductor device simulation system using region graph. The semiconductor device simulation system comprises: a region graph generation module for generating a region graph using a device structure file of a semiconductor device to be simulated; a device determination module for determining a type of semiconductor device for the region graph using a trained graph artificial neural network; an initial solution generating module for generating an initial solution for a device structure corresponding to the type of semiconductor device; and a semiconductor device simulator for performing semiconductor device simulation using the initial solution. The semiconductor device simulation system accelerates the speed of performing semiconductor device simulation by providing an approximate initial solution to the device structure to a semiconductor device simulator.

To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.

A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.

Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

An apparatus to facilitate transparent network access controls for spatial accelerator device multi-tenancy is disclosed. The apparatus includes a secure device manager (SDM) to: establish a network-on-chip (NoC) communication path in the apparatus, the NoC communication path comprising a plurality of NoC nodes for ingress and egress of communications on the NoC communication path; for each NoC node of the NoC communication path, configure a programmable register of the NoC node to indicate a node group that the NoC node is assigned, the node group corresponding to a persona configured on the apparatus; determine whether a prefix of received data at the NoC node matches the node group indicated by the programmable register of the NoC; and responsive to determining that the prefix does not match the node group, discard the data from the NoC node.