The present invention relates to an optical biometric sensor comprising: a read-out circuitry controllable for converting analog sensing signals to digital signals, the analog sensing signals being indicative of an image acquired by an image sensor comprising an array of photodetectors; and a timing circuitry configured to control the read-out circuitry to provide digital signals based on a present data transfer capacity on a data transfer bus configured to transfer data indicative of the digital signals from the optical biometric sensor to a host device.

A method of providing diagnostics communication in a diagnostics electrical architecture of a vehicle, the vehicle comprising a plurality of on-board computing devices for hosting the diagnostics electrical architecture. The diagnostics electrical architecture comprises: one or more electronic control units each comprising a diagnostics server module; a service interface module arranged to allow diagnostic communication between the one or more electronic control units and a network service bus of the vehicle; and a diagnostic services registry module. The method comprising: performing, by the diagnostics server module, diagnostic tasks to generate diagnostic object data; receiving into the service interface module the generated diagnostic object data; retrieving diagnostic services data from the diagnostic service registry module, the diagnostic services data comprising diagnostic capability descriptions of the generated diagnostic object data; and transmitting a diagnostic service notification over the network service bus, the diagnostic service notification being based on the generated diagnostic object data and the diagnostic services data.

The present invention provides a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer of different communication rates. The present invention includes: a FIFO that inputs a first clock of a first frequency, first transmission data based on the first clock, and a second clock of a second frequency which is different from the first frequency, and that outputs the first transmission data on the basis of the second clock in the order of input; a flipflop that fetches and holds the FIFO output on the basis of the second clock; and an output state machine operating with the second clock that inputs the FIFO output and the flipflop output, and generates parallel data in which the same data corresponding to the first transmission data is consecutive.

A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

The document describes systems and methods for handling local (legacy) devices. A local cloud gateway comprises a plurality of interface connectors of different types to physically connect a plurality of these legacy devices to the cloud, comprising a plurality of distant servers. Developments describe the step of extracting the functional messages out of messages stemming from local legacy devices (e.g. protocol translators), secure communications, logical representations of legacy devices in the cloud (“twins”), administration options, various user interfaces (e.g. buzzer) for seamless configuration and use, the use of one or more actuators (retroactions on the physical world), etc. Software and/or hardware embodiments are described.

Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

Various embodiments comprise systems, mechanisms, methods and apparatus configured to regenerate or recreate a stream of substantially continuous serial bus data traffic using stored data packet sequences representing captured energy associated with inverting and non-inverting communication lines of a differential transmission line type of serial bus (e.g., RS-422, MIL STD 1553, and the like).

Systems and methods for implementing a user mode virtual serial communications port emulator are disclosed herein. According to an aspect, a method for a virtual serial communications port emulator includes using at least one processor and memory for creating a virtual serial communication port (VCP) driver in a user mode of an operating system. The method further includes emulating a physical serial communication port using the VCP driver. In addition, the method includes converting outgoing data from an application executed on the at least one processor and memory via the VCP driver into a format complying with a protocol associated with a VCP device server. The method also includes converting incoming data from the VCP device server complying with the protocol into a second format understood by the application, wherein the VCP driver is communicated with using an unpublished universally unique identifier (UUID).