A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

The purpose of the present invention is to cause a reception side communication device to appropriately detect a start bit. A serial communication unit (100), which transmits serial data by a combination of a high level signal and a low level signal, is provided with: a serial communication part (111) that provides the start bit on the head of the serial data, and transmits the high level signal in a prescribed duration just before the start bit; and a duration setting part (113) that sets the duration.

A host device of a serial device system having a serial communications connection The host device including a host serial communication transceiver connected to a peripheral serial communication transceiver of a peripheral device via a serial connection of a serial communications cable having communication lines. The host device measures electrical power consumption of the host serial communication transceiver to determine when serial communications is prevented due to the serial communications cable being disconnected which includes at least one of the communication lines being detached from the host, detached from the peripheral device, or broken.

A memory system includes a nonvolatile memory and a serial peripheral interface (SPI) controller communicable with an external controller external to the memory system in accordance with an SPI standard, a first terminal through which the SPI controller receives a command, and a second terminal. The SPI controller is configured to operate in one of a plurality of operational modes in accordance with the command received through the first terminal. The operational modes include a first mode in which a signal received through the second terminal is used as a control signal to perform a predetermined function and a second mode in which the signal is not used as the control signal to perform the predetermined function.

Disclosed are techniques for using firmware and hardware blocks of a device to decode signals encoded by signal edge positioning within a data bit width, such as bi-phase mark space coding (BMC) used for encoding in-band communication of wireless charging systems. The first device may use general purpose I/O (GPIO) interrupts to detect the start of a packet. The firmware may synchronize and configure the clock of a serial peripheral interface (SPI) to oversample the signals. The SPI may store the sampled data into a buffer, freeing the firmware from having to expend processing cycles to detect the transitions of the data in real-time. The firmware may read the buffered samples to decode the packet data in a post-processing stage. The firmware may detect the end of the packet by polling and GPIO interrupts or based on the samples read from the buffer to stop the clock of the SPI.

The present disclosure provides a high-frequency magnetoimpedance testing apparatus and method. A testing platform in the apparatus is arranged within a Helmholtz coil and connected to a modulating electric current source and a high-frequency impedance analyzer, respectively; the Helmholtz coil is connected to a DC power source; a processor is connected to the high-frequency impedance analyzer and the DC power source separately; the testing platform includes a first double-sided copper-clad plate, and mode transition switches and connection terminals that are arranged on the first double-sided copper-clad plate; one end of the first double-sided copper-clad plate is connected to the high-frequency impedance analyzer, while the other end of the same is connected to a load; the mode transition switches are connected to the modulating electric current source. The present disclosure can realize in-situ current modulation of metallic fibers and high-frequency magnetoimpedance testing, and improve the testing accuracy.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.