Embodiments of an N-channel serial peripheral interface are described, and N-channel serial communication links comprising the same. Also described are methods of communication using N-channel serial communication interfaces and links.

An access control apparatus is provided. The apparatus can be used to unlock a device, wherein the device has a computation unit and at least one operator control unit that is electrically connectable to the computation unit, wherein the apparatus has a first reception unit for receiving electrical signals from the at least one operator control unit, a transmission unit for transmitting the electrical signals to the computation unit, a second reception unit for receiving at least one access message transmitted by means of an electromagnetic signal, an authorization unit for generating a switching signal if the result of the check on the access message is that unlocking of the device is permitted by means of the access message, and an unlocking unit for unlocking a transmission of electrical signals from the first reception unit to the transmission unit on the basis of the switching signal.

Disclosed are a method and a device for controlling a serial interface of a wireless earphone, a wireless earphone, and a computer readable storage medium. The method includes: disabling a serial interface function of the wireless earphone in a case that a first predetermined condition is met, where the first predetermined condition includes that the wireless earphone is outside a charging case, or the wireless earphone is in the charging case and a lid of the charging case is closed; and enabling the serial interface function of the wireless earphone in a case that a second predetermined condition is met, where the second predetermined condition includes that the wireless earphone is in the charging case and the lid of the charging case is open.

The invention provides a system capable of remotely maintaining the operation of electronic apparatus. The system comprises a cloud management platform and at least one electronic apparatus. The electronic apparatus comprises a data storage device and an operating system maintenance device. The data storage device comprises a plurality of flash memories and a controller. The operating system maintenance device comprises a microprocessor and a network communication component. An operating system is installed in the flash memories of the data storage device. When the operating system of the electronic device is abnormal, the operating system maintenance device receives an operating system repairing instruction from the cloud management platform via the network communication component. The microprocessor of the cloud management platform repairs the operating system of the electronic apparatus according to the operating system repairing instruction, so that the operating system of the electronic apparatus can resume normal operation.

A microcontroller is provided with a plurality of slave drive units for driving peripheral devices. Individual speed units are provided that have serial shift registers, multiplexors, and duplex data communication connections with individual serial registers of respective slave drive units of a series chain. In a first cycle or mode, a serial data connection between the serial shift registers of the speed units causes data to be serially communicated, at a first relatively faster pulse rate, from the microcontroller into the data input of the series chain and to the microcontroller from the data output of the series chain. In a second cycle or mode, for each pair of single speed unit and slave drive unit, the duplex data communication between the serial shift registers of the pair causes, at a second relatively slower pulse rate, data to be serially communicated in parallel therebetween.

Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.