A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

A method for monitoring automatic mechanical devices selected from at least one of automatic doors and automatic dock equipment located at a commercial site. The method may include installing, at the commercial site, a plurality of internet-of-things (IoT) monitoring devices. Each of the IoT monitoring devices may include a plurality of connectors corresponding to respective data communication standards, and a wireless transceiver configured to transmit operational information. Electronic communication between each automatic mechanical device and one of the IoT monitoring devices may be established via one of the connectors. A device profile may be assigned for each of the automatic mechanical devices. Each device profiles defines a respective connector and combination of manufacturer and device model. Data reflecting operational events and states of the automatic mechanical devices is received over the connectors, and corresponding operational information relating to the automatic mechanical devices is transmitted for analysis.

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

A hardware serial adapter that can be connected to a serial port of a physical computing device and is associated with network credentials that include a unique hardware identifier and other security information. Upon receipt of data (or other initiation command), the hardware serial adapter transmits a registration request with the network credentials to a distributed network service. If the network credentials are valid, the network service provides communication channel configuration information and session credentials to establish a secure communication for the transmission of data from the hardware serial adapter to a virtual machine instance. The distributed network service can control and manage data transmissions and the communication channel.

A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

A method for controlling a serial port information of a server host is provided. At first, a basic input/output system of the server host is activated. Then the BIOS reads a first port state value of a first input/output port of a MOS chip. Then an information output state of a serial port of a server host is determined according to the first port state value of the first input/output port, wherein the information output state is related to whether to output information of the serial port.

The invention provides a system capable of remotely controlling electronic apparatus. The system comprises a cloud management platform and an electronic apparatus. The electronic apparatus comprises a motherboard and a data storage device. The motherboard comprises a standby power circuit. A standby power is supplied to the data storage device via the standby power circuit. The data storage device comprises a data storage unit and a program management unit. The program management unit comprises a microprocessor and a network communication component. Whether the electronic apparatus is in a power-on state or a power-off state, the data storage device can always maintain in a normal operation via the standby power. When the microprocessor of the program management unit receives a specific operation instruction from the cloud control platform, it will execute a corresponding operation program according to the specific operation instruction.