A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.

A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T.sub.1 . . . T.sub.4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T.sub.1 . . . T.sub.4 at least one of the four signals has an edge to enable clock recovery at the second IC.

A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

A speech recognition device includes a voice collection module configured to collect voices; a voice denoising module electrically connected to the voice collection module and configured to denoise the collected voice; a voice recognition module electrically connected to the voice denoising module and configured to recognize voices denoised by the voice denoising module and converted the denoised voices into control instructions; an interface conversion module electrically connected to the voice recognition module and configured to convert the control instructions into digital signals; and a parallel port interface electrically connected to the interface conversion module and configured to be inserted into an electronic device so that the digital signals can be transmitted to the electronic device via the parallel port interface. The present invention provides a new speech recognition device and system to fast response to simple operation instructions without cloud recognition operation.

According to one embodiment, a magnetic disk device includes a control device and a regulator device. The control device and the regulator device are connected to each other through a first interface and a second interface. The control device transmits a required voltage value to the regulator device through the first interface and transmits a correction value based on the required voltage value and an output voltage output from the regulator device to the regulator device. The regulator device outputs a voltage to the control device on the basis of the received required voltage value and corrects a value of the voltage to be output to the control device on the basis of the received correction value.

A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.