A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.

Approaches in accordance with various embodiments provide for the management of system event data in a computing device. In particular, various embodiments provide an intelligent persistent buffer for system event log (SEL) messages. A SEL message can be generated by system BIOS on a computing device, which can send this message over an appropriate interface to a target recipient, such as the BMC. Instead of being received directly to the BMC, however, the SEL message can be received to a logic device, such as a CPLD, that is able to analyze the message, determine that the message relates to an important system event, and can cause this message to be stored to a persistent buffer. The BMC can then subsequently request the buffered SEL message from the logic device to take an appropriate action.

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.

An accessory and an electronic device capable of suppressing malfunction and failure of the accessory when a command to be executed by the accessory is transmitted from the electronic device to the accessory and reducing the memory capacity. The accessory is communicably connected to the electronic device. The accessory includes a communication unit that communicates with the electronic device, a storage unit that allows reading therefrom and writing therein and stores a flag indicating whether execution of a command by the accessory is allowed or not, a control unit that, upon receipt of a predetermined command from the electronic device, does not execute the predetermined command in a case where the flag indicates that execution of the command is not allowed, and executes the predetermined command in a case where execution of the command is allowed.

Methods and apparatus for providing validation of data from the tracker devices. In embodiments, a method includes registering a tracker device with a device registry and issuing by an issuer the tracker device to a third party. Raw and signed data is collected from the tracker device is hashed and stored to enable later validation of the data.

A bus arbitration circuit includes a first bus port, a second bus port, a first output circuit connected to the first bus port, a second output circuit connected to the second bus port, a control circuit, and a switch circuit. The control circuit includes a first input port, a second input port, a control signal output port, and an output port. The first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port to an input port of the first output circuit. The switch circuit has an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of a host bus is outputted to an input port of the second output circuit.

A time domain duplex (TDD) device is disclosed. The TDD device may include at least a digital interface and a TDD physical interface (PHY). The digital interface may be coupled to a plurality of peripheral devices. The TDD PHY may be coupled to a micro-coaxial cable. The TDD device may aggregate data from the plurality of peripheral devices and transmit the aggregated data through the TDD PHY.

An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.