G06F2213/0024

Systems and methods for data transfer over a shared interface
11620250 · 2023-04-04 · ·

A method for compressing is provided. The method includes compressing, via a processor, a portion of a first data packet to generate a second data packet having a compressed portion. The method includes transmitting the second data packet having the compressed portion via an interface to a co-processor. The processor and the co-processor are communicatively coupled via the interface. The method also includes unpacking, via the co-processor, the compressed portion of the second data packet to restore the first data packet.

Procedures for improving efficiency of an interconnect fabric on a system on chip

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

PACKET CONTROL APPARATUS AND PACKET CONTROL METHOD
20230185756 · 2023-06-15 · ·

A packet control apparatus includes a transmission source device configured to add processing wait information that indicates whether to permit immediate processing to a packet to be transmitted to a destination, and a transmission target device configured to, in a case where the processing wait information is added to the packet, wait for and receive a processing permission notification that indicates a completion of a preceding packet from the transmission source device, and process the packet, the transmission target device being a device of the destination, wherein the transmission source device and the transmission target device are coupled to each other through a bus.

Generic Packet Header Insertion and Removal
20220377014 · 2022-11-24 ·

A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

FIRMWARE RETRIEVAL AND ANALYSIS
20230177162 · 2023-06-08 ·

A bus filter driver and security agent components configured to retrieve and analyze firmware images are described herein. The bus filter driver may attach to a bus device associated with a memory component and retrieve a firmware image of firmware stored on the memory component. The bus filter driver may also retrieve hardware metadata. A kernel-mode component of the security agent may then retrieve the firmware image and hardware metadata from the bus filter driver and provide the firmware image and hardware metadata to a user-mode component of the security agent for security analysis. The security agent components may then provide results of the analysis and/or the firmware image and hardware metadata to a remote security service to determine a security status for the firmware.

CONTROL METHOD, ELECTRONIC DEVICE, AND WRITING INTERACTION DEVICE
20230170745 · 2023-06-01 ·

A control method includes in response to a predetermined contact event between a writing interaction device and an electronic device, performing, by the electronic device, a charging protocol adaptation process on the writing interaction device to obtain a target charging protocol to be adopted, performing a charging process for the writing interaction device based on the target charging protocol, and obtaining one or more communication protocol parameters transmitted by the writing interaction device using the target charging protocol during the charging process, identifying a target communication protocol adopted by the writing interaction device based on the one or more communication protocol parameters, and controlling the target communication protocol to take effect on the electronic device to communicate with the writing interaction device based on the target communication protocol in response to the electronic device receiving an interaction operation of the writing interaction device.

Device full memory access through standard PCI express bus

A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

EMBEDDED PHYSICAL LAYERS WITH PASSIVE INTERFACING FOR CONFIGURABLE INTEGRATED CIRCUITS

Disclosed herein are devices and systems that embed a physical layer (e.g., an M-PHY) on a configurable integrated circuit (e.g., an FPGA) and include glue hardware that provides AC coupling between a high-speed serial communication device (e.g., a MIPI device) and the configurable integrated circuit. The glue hardware provides AC coupling using only resistors, capacitors, and inductors. The configurable integrated circuit includes a logic block that manages the operation to provide the desired PHY connectivity. Because the disclosed devices and systems use AC coupling, the signaling drive and receive paths are controlled based on the received signal frequency and not based on the mode (e.g., LS mode or HS mode). Specifically, the line state of the MIPI device is inferred from observation of signal transitions as opposed to direct detection of DC signal levels.

TRANSMITTING UNIVERSAL SERIAL BUS (USB) DATA OVER ALTERNATE MODE CONNECTION

An example includes an apparatus for transmitting Universal Serial Bus (USB) packets. The apparatus includes a transmitter adapter to receive a USB packet from a USB device. The transmitter adapter can further generate one or more alternate mode packets based on the USB packet. The transmitter adapter can also transmit the alternate mode packets via an alternate mode connection.

MULTIPLE INPUT-OUTPUT MEMORY MANAGEMENT UNITS WITH FINE GRAINED DEVICE SCOPES FOR VIRTUAL MACHINES
20170249106 · 2017-08-31 ·

A system and method of emulated input-output memory management units includes a management software associating a first device with a first input-output memory management unit having a first security designation, and associating a second device with a second input-output memory management unit having a second security designation different from the first security designation. A hypervisor constructs a table that describes associations between the plurality of devices and the plurality of input-output memory management units. The hypervisor provides the table to a guest virtual machine having a plurality of guest addresses including a first guest address and a second guest address. The first device accesses the first guest address through the first input-output memory management unit and the second device accesses the second guest address through the second input-output memory management unit.