An apparatus includes an interface with a plurality of channels; a multiplexer coupled to the interface and configured to couple transmit circuitry to a first channel mapped as a transmit path in a channel configuration and to couple receive circuitry to a second channel mapped as a receive path in the channel configuration; and a controller coupled to the multiplexer. The controller may be configured to perform the steps including determining a figure of merit of at least one channel of the plurality of channels of the interface; determining the channel configuration mapping transmit and receive paths to the plurality of the channels of the interface; and controlling the multiplexer to couple transmit circuitry to the first channel mapped as a transmit path in the channel configuration and to couple receive circuitry to the second channel mapped as a receive path in the channel configuration for dynamic channel swap(s).

Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

A Dynamic Peripheral Component Interconnect Express (PCIe) speed-adjusting method is provided. The dynamic PCIe speed-adjusting method is applied to a wireless device. The dynamic PCIe speed-adjusting method may include the following step: the wireless device determines whether to change from the current PCIe speed to a target PCIe speed based on the noise level threshold, the signal-to-noise ratio (SNR) threshold, the current data-rate requirement, or a combination thereof.

A PCIe resource management system includes a PCIe resource registration subsystem and a PCIe resource monitoring subsystem. Assets register to use PCIe resources of other assets and to allow other assets to use their PCIe resources. Assets specify which types of PCIe resources it can borrow, when it can borrow those PCIe resources, and a logical group of other assets from which the asset can borrow the PCIe resources. Assets also specify which types of PCIe resources it will lend, when it will lend those PCIe resources, and a logical group of other assets to which the asset will lend the PCIe resources. The PCIe resource registration subsystem maintains a PCIe resource registration datastore maintaining PCIe borrow and lending rules associated with assets in logical groups of assets. PCIe resources are shared between assets in the logical groups as needed, as determined by the PCIe resource monitoring subsystem.

An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

The present application discloses a display panel and a display device. The display panel includes: a common electrode layer including a plurality of columns of first common electrodes, wherein each column of the plurality of columns of the first common electrodes includes a plurality of touch electrodes insulated from each other; and a driving module. Each of the plurality of touch electrodes is electrically connected to the driving module through one or more touch leads. A number of the touch leads corresponding to each of or adjacent ones of the plurality of touch electrodes gradually increases along a direction away from the driving module.

A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.

A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.