A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

A storage drive adapter may comprise an adapter board, which may include a first and second carrier module interface to removably engage with a first and a second storage drive carrier module, respectively. The adapter board may further include a dual ported storage drive connector to engage with a complementary storage drive bay interface. The dual ported storage drive connector may include a first port to provide a first signal path from the complementary storage drive bay interface to the first carrier module interface. Similarly, the dual ported storage drive connector may also include a second port to provide a second signal path from the complementary storage drive bay interface to the second carrier module interface.

In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

A storage device comprises tape reel(s) holding tape media for storing data, a head assembly, motor(s) configured to actuate the head assembly, a sealed casing, and a printed circuit board assembly (PCBA) configured to control operations of the motor(s). The head assembly comprises a support structure, a head bar with read head(s) and write head(s), and a suspension system connecting the head bar to the support structure. The sealed casing encloses in its interior the tape reel(s), the head assembly, and the motor(s). Meanwhile, the PCBA is mounted on an external surface of the casing.

Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Provided is a module mounted in a server to share a block-level storage and resources. The module includes: a HBA card unit for connection to an external server; an internal disk unit providing a storage space inside a server; a setting unit allocating the storage space of the internal disk unit; a target driver unit implementing a SCSI protocol, communicating with the external server and setting volumes to a storage mode or a server mode; and a target core unit routing data of the internal disk unit and the target driver unit depending on the storage mode or the server mode. The storage mode allows the volumes to be used as a storage of the external server. The server mode allows the volumes to be used as a storage inside the server. The target driver unit can switch the volumes from the server mode to the storage mode.

A RAID storage management system includes a plurality of RAID storage devices and a controller configured to manage the plurality of RAID storage devices. The RAID storage management system also includes at least one expander operatively connected to the controller and operatively connected to the plurality of RAID storage devices. The expander is configured to receive a request from the controller for a RAID operation. The expander is also configured to, upon receiving the request, operate to assist the controller in performing the requested RAID operation.

An electronic device includes an interface with a first terminal, a second terminal, and a power supply. A voltage divider includes series-connected resistors, between the first terminal and ground voltage. A first programmable fuse is provided and the voltage divider converts the first signal to a different voltage level according to the state of the first programmable fuse. A first transistor has a gate receiving the converted first signal and a second transistor has a gate electrically connected to the second terminal and a source-drain terminal of the first transistor. The second transistor is off when the first transistor is on. A fuse-type switching element is connected between the power supply terminal a power supply circuit. A control terminal of the fuse-type switching element is connected to a source-drain terminal of the second transistor switches conduction state according to whether the second transistor is on or off.