According to an embodiment of the disclosure, an electronic device comprises: a battery, a memory, a connector including one or more signal terminals, a first converter included in a first path that connects the battery to the connector, a second converter included in second path that is distinct from the first path and connects the battery to the connector, and a processor electrically connected to the battery, the memory, the connector, the first converter, and the second converter, wherein the memory stores instructions that, when executed, cause the processor to obtain identification information of the external electronic device when the electronic device is connected to the external electronic device through the connector, determine whether the identification information matches comparison data stored in the memory, determine whether a voltage of a power terminal (vbus) among the one or more signal terminals satisfies a specified condition when the identification information matches the comparison data, and transmit power determined based on a real-time voltage of the battery to the external electronic device by using the second path through the connector, based on whether the specified condition is satisfied.

Disclosed herein is a universal serial bus port controller on a source side. The universal serial bus port controller is compatible with universal serial bus Type-C. A source is equipped with the universal serial bus port controller including a power supply terminal, a power supply circuit, a switch connected between an output of the power supply circuit and the power supply terminal, a capacitor connected to the power supply terminal, and a discharge resistance and a discharge switch connected in series with each other between the power supply terminal and a ground line. The universal serial bus port controller includes an abnormality detector which detects an output voltage of the power supply terminal a plurality of times after the discharge switch is turned on and detects an abnormality on the basis of a temporal change in the output voltage.

A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

A docking station and a control method thereof are provided. The docking station includes a first USB interface, a second USB interface, a video signal output terminal, a microcontroller, a first signal multiplexer, a second signal multiplexer, a video signal processor, and a video signal converter. The microcontroller determines whether the first USB interface or the second USB interface is connected to an electronic device. When the first USB interface is connected to the electronic device, the microcontroller sets the first USB interface as an uplink port. The uplink port receives a signal from the electronic device, and selects and outputs a video signal through the signal. The video signal processor is configured to receive and process the video signal. The video signal converter converts the video signal into a video output signal that is capable of being output to the video signal output terminal for playing.

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.

The present disclosure provides a mobile power supply and a method for supplying power to a peripheral device. The mobile power supply comprises a first peripheral connection port and a second peripheral connection port, a first group of connection-port processing circuits and a second group of connection-port processing circuits, a control circuit, and a power supply circuit. A control strategy determining circuit in each group of connection-port processing circuits determines a voltage adjustment strategy according to power supply status information of a corresponding peripheral connection port. The control circuit then causes a voltage adjusting circuit in the connection-port processing circuit to adjust, according to the voltage adjustment strategy, a voltage output by the power supply circuit, such that the adjusted voltage is used to supply power to a peripheral device coupled, by means of a power supply terminal, to the peripheral connection port.

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

The present disclosure relates to an interface comprising: a terminal for delivering a DC voltage; a comparator for delivering a first signal representative of a comparison of the DC voltage with a high threshold; a comparator for delivering a second signal representative of a comparison of the DC voltage with a low threshold; and a circuit configured to: deliver successive pairs of values of high and low thresholds for a time period after the DC voltage crosses a first value of the low threshold; modify successive pairs of values of the thresholds based on the first and second signals to determine values of thresholds surrounding the DC voltage; and determining a current value of the DC voltage based on the values of thresholds surrounding the DC voltage.

In one aspect, an apparatus may include a processor and a communication interface accessible to the processor. The communication interface may be configured to communicate with a computing device. The apparatus may also include storage that is accessible to the processor and that includes instructions executable by the processor to monitor a circuit within the computing device to detect a break in the circuit. The circuit itself may be completed based on the apparatus being engaged with the computing device. Responsive to detecting a break in the circuit, the instructions may then be executable to write first data to at least one log stored on the apparatus. The instructions may also be executable to monitor the computing device to detect the computing device being powered on and, responsive to detecting the computing device being powered on, write second data to the at least one log stored on the apparatus.

A biometric token is generated for a user and provided to a user-operated device. A pre-staged transaction is defined by a user and the user supplies the token for association with the pre-staged transaction. Subsequently, a user visits a transaction terminal and a new candidate token is generated from biometric attributes of the user. The candidate token is matched to the token associated with pre-staged transaction to authenticate the user and the pre-staged transaction is processed at the transaction terminal as a completed transaction.