A power amplification module includes first and second amplifiers for first and second communication modes, a bypass line that bypasses the first or second amplifier, an input switch circuit that supplies a radio frequency signal to the first or second amplifier in accordance with a communication mode when a desired output level is equal to or greater than a reference level and supplies a radio frequency signal to the bypass line when the desired output level is less than the reference level, and an output switch circuit that outputs a first amplified signal from the first amplifier or a second amplified signal from the second amplifier in accordance with the communication mode when the desired output level is equal to or greater than the reference level and outputs a radio frequency signal output from the bypass line when the desired output level is less than the reference level.

A high-gain, low power, electronic amplifier for amplification of a low magnitude voltage signal through a comparator-integrator amplification method for energy-aware applications is disclosed. The electronic amplifier comprises: a comparator arrangement with at least one comparator unit adapted to receive a first voltage signal to be amplified and a first feedback voltage signal, and to generate a first two-level voltage comparison signal; a integrator arrangement to receive the first two-level voltage comparison signal and generate a first amplifier output signal corresponding to an amplification of the voltage signal to be amplified; and a first feedback network to receive the first amplifier output signal and generate the first feedback voltage signal.

A signal processing circuit has a first mixer, a first amplifier, and a pulling effect mitigation circuit. The first mixer mixes a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor. The first amplifier amplifies the first output signal, and generates an amplified output signal at an output terminal of the first amplifier. The pulling effect mitigation circuit is coupled to the output terminal of the first amplifier, and generates a compensation signal to the output terminal for reducing at least an N.sup.th harmonic of the amplified output signal, wherein a value of N is equal to the frequency dividing factor.

The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.

A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

Provided is a power amplification module that includes: an amplification transistor that has a constant power supply voltage supplied to a collector thereof, a bias current supplied to a base thereof and that amplifies an input signal input to the base thereof and outputs an amplified signal from the collector thereof; a first current source that outputs a first current that corresponds to a level control voltage that is for controlling a signal level of the amplified signal; and a bias transistor that has the first current supplied to a collector thereof, a bias control voltage connected to a base thereof and that outputs the bias current from an emitter thereof.

In the example of a voltage regulator outputting a negative voltage, its feedback voltage will also be negative. The feedback voltage is typically created using a resistor divider. A controller IC is powered by only a positive voltage and receives the negative feedback voltage at a high impedance input of an inverting amplifier. Therefore, the inverting amplifier does not load the resistor divider, resulting in an accurate regulated output voltage. The inverting amplifier converts the negative feedback voltage to a positive feedback voltage for further processing by the controller IC. An error amplifier and a power good monitor receive both the original feedback voltage and the inverted feedback voltage and use whichever feedback voltage is the more positive one. Therefore, the controller IC may be used in voltage regulators that generate either negative or positive output voltages.

Embodiments of a mixer of a Near field communication (NFC) receiver device and a method for operating a mixer of an NFC receiver device are disclosed. In an embodiment, a mixer of an NFC receiver device includes an input unit from which an input signal is received, a sample and hold circuit configured to sample the input signal and to store electrical charge based on the sampled input signal in order to generate a differential output signal, a control unit configured to switch the sample and hold circuit between different operational modes based on whether the input signal is a single-ended input signal or a differential input signal, and a differential output unit from which the differential output signal is output. Other embodiments are also described.