Systems, methods, and non-transitory media are provided for dynamically switching frame rates without changing a display refresh rate. An example method can include receiving, from a display device associated with a computing device, a set of control signals indicating a display refresh rate implemented by the display device; adjusting a frame rate associated with application data from one or more applications executed on the computing device; synchronizing, based on the set of control signals, the adjusted frame rate with two or more display refresh cycles, each display refresh cycle being based on the display refresh rate; providing, to the display device, a first frame at the adjusted frame rate, the first frame being generated based on the application data; and displaying the first frame at the display device implementing the display refresh rate.

Systems, methods, and non-transitory media are provided for dynamically switching frame rates without changing a display refresh rate. An example method can include receiving, from a display device associated with a computing device, a set of control signals indicating a display refresh rate implemented by the display device; adjusting a frame rate associated with application data from one or more applications executed on the computing device; synchronizing, based on the set of control signals, the adjusted frame rate with two or more display refresh cycles, each display refresh cycle being based on the display refresh rate; providing, to the display device, a first frame at the adjusted frame rate, the first frame being generated based on the application data; and displaying the first frame at the display device implementing the display refresh rate.

A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Embodiments of this application provide a control method based on a vertical synchronization signal and an electronic device, to shorten a response delay of the electronic device and improve fluency of the electronic device without increasing load of the electronic device. The method may include: drawing, by an electronic device including a display screen, one or more layers in response to a first vertical synchronization signal; refreshing and displaying an image frame in response to a second vertical synchronization signal; adjusting the first vertical synchronization signal, so that the adjusted first vertical synchronization signal is delayed by first delay time relative to the second vertical synchronization signal; and drawing one or more layers in response to the adjusted first vertical synchronization signal.

A driving circuit that includes a timing controller, a selecting module connected to the timing controller, and a level shifter connected to the selecting module, wherein the timing controller includes N pins, each of the pins provides a clock signal, and N is a positive integer; the selecting module includes N selecting units, an input terminal of each of the selecting units is connected to a corresponding pin of the timing controller, output terminals of each of the selecting units are connected to M input pins of the level shifter, and M is greater than or equal to 2. The driving circuit according to the present invention individually passes clock signals of a timing controller through selecting units and outputs to a level shifter, and pins of the timing controller can be substantially saved.

An overcurrent protection circuit includes: a sampling sub-circuit configured to acquire gate input signals, select a gate input signal with a voltage value greater than a first preset voltage value as a sample gate input signal, generate a first control signal according to the sample gate input signal, and output the first control signal; a delay determination sub-circuit configured to receive the first control signal, delay the first control signal for a first preset time, determine whether a voltage value of the first control signal after delay is less than a voltage value of the first control signal before the delay, and if not, output a counting signal; and a counting control sub-circuit configured to receive the counting signal, perform counting according to the counting signal, and if a counted number reaches a preset number, output a second control signal.

A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

A driving method of a display panel is provided, by pre-storing a new setting information of a source output enable signal in a peer-to-peer protocol, and detecting a default setting information of the source output enable signal, and according to a detection result of the default setting information, invoking the new setting information when switching different drivers, a setting information of the source output enable signal in the peer-to-peer protocol can be unified, thereby avoiding the charging time difference due to a replacement of drivers.

A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.