The present invention provides a gate driver on array (GOA) circuit, a display panel, and a threshold voltage compensating method for a thin film transistor (TFT). The GOA circuit only includes five TFTs and achieves a super narrow bezel of a display panel, and uses a dual-gate electrode structure as the first thin film transistor (T1). Therefore, a threshold voltage (Vth) in the GOA circuit is controlled by a top gate (the top gate connected to a node in the GOA circuit) and a bottom gate (adjustable voltage source (VLS)). Specifically, when the Vth of the TFT negatively shifts overall, the bottom gate voltage can be adjusted negatively. When the Vth of the TFT positively shifts, the bottom gate voltage can be adjusted negatively to stabilize the GOA circuit, increase a lifespan thereof, reduce leakage of a first node (Q) such that the GOA circuit can output ultra-wide pulse signals.

A bi-stable electronic display driving technique drives an image refresh on a bi-stable electronic display, such as an electrophoretic display, using a driving integrated circuit with a single and limited in size image buffer, in a manner that does not require a simultaneous blanking or erasing of the display and in a manner that operates to drive the pixel elements of the display to their final value associated with the new image more quickly during an image refresh cycle. This technique results in an image refresh that is of higher quality and that is more pleasing to the eye while still using a driving integrated circuit with limited memory and processing power.

A display includes a plurality of pixels. The pixels include at least one emitter unit. The emitter units each include a primary emitter and a secondary emitter for generating light of the same color. The secondary emitter is associated with the primary emitter of the corresponding emitter unit. The primary emitters and the secondary emitters are based on at least one semiconductor material. The emitter units each include a correction circuit. The correction circuits are each configured to be able to switch the generation of light from the primary emitter to the associated secondary emitter in case of a defect of the associated primary emitter.

A display device includes a first substrate, a wire pad in a pad area, first banks in a display area, electrodes on the first banks, a pad electrode base layer on the wire pad, having a greater width than the wire pad, and covering sides of the wire pad, a first insulating layer covering parts of the electrodes and part of the pad electrode base layer, light-emitting elements on the first insulating layer in the display area, respective ends of the light-emitting elements being on different electrodes, contact electrodes on the electrodes and contacting first ends of the light-emitting elements, and a pad electrode upper layer on the first insulating layer in the pad area and directly contacting the pad electrode base layer, wherein the pad electrode base layer includes the same material as the electrodes, and the pad electrode upper layer includes the same material as the contact electrodes.

Provided are a display panel and display device. The display panel includes a driver circuit, where the driver circuit includes an N-stage cascaded shift register which includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to control a signal of a second node. The third control unit is configured to receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node. The fourth control unit is connected to the third node.

A detection circuit, a method for driving the same, and a display device are provided. In an embodiment, the detection circuit includes driving circuits, signal reading lines, and a pre-configuration module. In an embodiment, one of the signal reading lines is coupled to at least two of the driving circuits. In an embodiment, the pre-configuration module is coupled to the signal reading lines, and configured to output a preset signal to the signal reading lines to pre-configure potentials on the signal reading lines.

The array substrate includes a substrate and at least one display pixel arranged on the substrate. The display pixel includes a plurality of first pixels and a plurality of second pixels arranged along a row direction and a column direction. The period along the row direction or the column direction includes three display pixels. Wherein within at least one period along the row direction and the column direction, the display pixel of the first row includes one second pixel and two first pixels adjacent to the second pixel. The display pixel of the second row includes one first pixel and two second pixels adjacent to the first pixel. The display pixel of the third row includes one first pixel and two second pixels adjacent to the first pixel, and the first pixel of the third row is in different column from the first pixel of the second row.

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.

A system and method of driving an electrowetting display device including a plurality of sub-pixels are presented. A sub-pixel in the plurality of sub-pixels is determined to be in an open state or a closed state and a target reflectance value is determined for the sub-pixel. For the sub-pixel in the open state, the target reflectance value is determined to be less than a first threshold value, and a reflectance value of the sub-pixel is set to either a minimum reflectance value or the first threshold value. For the sub-pixel in the closed state, the target reflectance value is determined to be less than a second threshold value, and the reflectance of the sub-pixel is set to either the minimum reflectance value or the second threshold value.

A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.