A sub-pixel for an LED display, the sub-pixel comprising a first light emitting device having a first emission beam angle and a second light emitting device having a second beam angle, the second emission beam angle being different to the first emission beam angle. There is also described a display using a plurality of the sub-pixels.

A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel comprising a switching element of a first type and a switching element of a second type different from the first type. The gate driver is configured to generate a gate signal based on a vertical start signal and a gate clock signal and output the gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission to the display panel. A driving frequency of the display panel is varied according to an input image. The gate clock signal has an active duration having a varied length according to the driving frequency.

A display apparatus includes a support substrate, a plurality of light emitting structures regularly arranged on the support substrate, and a wavelength conversion part disposed on the plurality of light emitting structures. The wavelength conversion part includes light transmitting portions and blocking portions, the light transmitting portions being disposed on the light emitting structures, respectively, and each of the light transmitting portions including a phosphor for converting a wavelength of light emitted from the corresponding light emitting structure. The support substrate includes a plurality of conductive patterns electrically connected to the light emitting structures, and the light emitting structures are coupled to the plurality of conductive patterns.

An electro-optically controlled active-matrix system comprises a system substrate, row wires extending in a row direction disposed on the system substrate, a row controller providing a row electrical signal to each row wire, column light-pipes extending in a column direction disposed on the system substrate, a column controller providing a column optical signal to each column light-pipe, and pixels disposed over the system substrate. Each pixel can comprise a pixel circuit that is uniquely responsive to a row wire and to a column light-pipe, the pixel circuit receiving the row electrical signal from the row wire and receiving the column optical signal from the column light-pipe. In some embodiments, column wires carrying column electrical signals extend in a column direction over the system substrate and the pixel circuit is capacitively coupled to the row wire, the column wire, or both.

A disclosed gate driver includes a plurality of stages, a k.sup.th stage comprising: a first output node connected to an emission line; a second output node; a Q node connected to a first controller and a pull-down circuit; the pull-down circuit and a pull-up circuit respectively controlled by the Q node and the second output node; the first controller configured to receive a voltage of a first output node of a (k−1).sup.th stage or a first start signal; a second controller configured to receive a voltage of a second output node of the (k−1).sup.th stage or a second start signal; a third controller configured to control the voltage of the second output node; and a fourth controller configured to be controlled by the second output node and to control the voltage of the first output node, wherein ‘k’ is a natural number ≥1.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

The disclosure is related to creating different functional micro devices by integrating functional tuning materials and creating an encapsulation capsule to protect these materials. Various embodiments of the present disclosure also related to improve light extraction efficiencies of micro devices by mounting micro devices at a proximity of a corner of a pixel active area and arranging QD films with optical layers in a micro device structure.

A display system includes (a) a display element having an organic light emitting diode-containing display active area disposed over a silicon backplane, (b) a display driver integrated circuit (DDIC) attached to the display element and electrically connected with the display active area, and (c) a thermal barrier disposed within the silicon backplane, where the thermal barrier is configured to inhibit heat flow through the silicon backplane and into the display active area.

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.

A display panel and a display device are provided. The display panel includes at least one pixel circuit and a light emitting element. One pixel circuit includes a driving transistor, a second transistor, a third transistor, and a first light-emission controlling module. The second transistor is connected between a data line and a source of the driving transistor and is configured to provide a data signal. The third transistor is connected between a voltage adjusting signal line and the source of the driving transistor and is configured to provide an adjusting voltage. The first light-emission controlling module is connected between a first power supply terminal and the source of the driving transistor and is configured to provide a power supply voltage. The power supply voltage provided by the first power supply terminal is VP, and the adjusting voltage is VJ, where VP<VJ≤VP+3.5V, and/or VP+1V<VJ.