Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

Disclosed herein is a sense amplifier. In one aspect, the sense amplifier includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier. In one aspect, the sense amplifier includes a first access transistor coupled between a first input line and the first port. In one aspect, the sense amplifier includes a second access transistor coupled between a second input line and the second port. In one aspect, the first pair of cross-coupled transistors includes a first transistor and a second transistor cross-coupled with each other. In one aspect, a source electrode of the first transistor is directly coupled to the first input line, and a source electrode of the second transistor is directly coupled to the second input line.

The present disclosure relates to the field of semiconductor circuit design, and in particular to a readout circuit layout structure and a method of reading data. The readout circuit layout structure includes: a first readout circuit structure and a second readout circuit structure having identical structures, wherein the first readout circuit structure and the second readout circuit structure each include: a first isolation module, configured to be turned on according to a first isolation signal, electrically connect a bit line and a first readout bit line, and electrically connect a complementary bit line and a first complementary readout bit line; a second isolation module, configured to be turned on according to a second isolation signal, electrically connect the first readout bit line and a second readout bit line, and electrically connect the first complementary readout bit line and a second complementary readout bit line.

The present disclosure relates to the field of semiconductor circuit design, and in particular to a readout circuit layout structure and a method of reading data. The readout circuit layout structure includes: a first readout circuit structure and a second readout circuit structure having identical structures, wherein the first readout circuit structure and the second readout circuit structure each include: a first isolation module, configured to be turned on according to a first isolation signal, electrically connect a bit line and a first readout bit line, and electrically connect a complementary bit line and a first complementary readout bit line; a second isolation module, configured to be turned on according to a second isolation signal, electrically connect the first readout bit line and a second readout bit line, and electrically connect the first complementary readout bit line and a second complementary readout bit line.

Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.