According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.

A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.

A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.

A method of making a physical unclonable function (PUF) having magnetic and non-magnetic particles is disclosed. Measuring both magnetic field and image view makes the PUF difficult to counterfeit. PUF may be incorporated into a user-replaceable supply item for an imaging device. A PUF reader may be incorporated into an imaging device to read the PUF. Other methods are disclosed.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

A ferromagnetic thin-film based digital memory having a plurality of bit structures interconnected with manipulation circuitry having a plurality of transistors so that each bit structure has transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that bit structure and permits selecting a direction of current flow through the bit structure if current is permitted to be established therein. A bit structure has a nonmagnetic intermediate layer with two major surfaces on opposite sides thereof and a memory film of an anisotropic ferromagnetic material on each of the intermediate layer major surfaces with an electrically insulative intermediate layer is provided on the memory film on which a magnetization reference layer is provided having a fixed magnetization direction.

A memory cell includes a VCMA magnetoelectric memory element and a two-terminal selector element connected in series to the magnetoelectric memory element.