A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.