Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.

A semiconductor device has stored therein a plurality of bits of fixed data. The semiconductor device includes a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output the value of each bit received at an input terminal of each of the memory elements according to a timing signal. An initialization control unit feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal, each of the plurality of memory elements being initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.

A semiconductor device has stored therein a plurality of bits of fixed data. The semiconductor device includes a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output the value of each bit received at an input terminal of each of the memory elements according to a timing signal. An initialization control unit feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal, each of the plurality of memory elements being initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.

A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

A 3D semiconductor device, the device including: a first level overlaid by a second level overlaid by a third level overlaid by a fourth level, where the second level includes an array of first memory cells, the first memory cells including first transistors, the first transistors including first sources, first gates, and first drains, where each of the first transistors includes a single the first source, a single the first gate, and a single the first drain, where the third level includes an array of second memory cells, the second memory cells including second transistors, the second transistors including second sources, second gates, and second drains, where each of the second transistors includes a single the second source, a single the second gate, and a single the second drain, where at least one of the first memory cells is self-aligned to at least one of the second memory cells, being processed following the same lithography step; vertically oriented word-lines adapted to control a plurality of the first gates and a plurality of the second gates; and horizontal drain-lines directly connected to a plurality of the first drains and a plurality of the second drains.

A 3D semiconductor device, the device including: a first level overlaid by a second level overlaid by a third level overlaid by a fourth level, where the second level includes an array of first memory cells, the first memory cells including first transistors, the first transistors including first sources, first gates, and first drains, where each of the first transistors includes a single the first source, a single the first gate, and a single the first drain, where the third level includes an array of second memory cells, the second memory cells including second transistors, the second transistors including second sources, second gates, and second drains, where each of the second transistors includes a single the second source, a single the second gate, and a single the second drain, where at least one of the first memory cells is self-aligned to at least one of the second memory cells, being processed following the same lithography step; vertically oriented word-lines adapted to control a plurality of the first gates and a plurality of the second gates; and horizontal drain-lines directly connected to a plurality of the first drains and a plurality of the second drains.

A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

An anti-fuse memory unit circuit, an array circuit and a reading and writing method are disclosed. The advantages of the device and method include: 1. the anti-fuse memory cell circuit is a pure combinational circuit, compared to time sequence circuit, after a delay of a certain time, this disclosed device closes all paths and stops the logic action of entire circuit, thus lowering the static power consumption to approximately 0; 2. this circuit constituted two positive feedback loops through the design of a switch and a logic calculation module, which enables its readout circuit to read 0 or 1 more reliably; 3. this circuit can eliminate a complicated timing sequence control part, even output the anti-fuse codes directly without latching the readout circuit output OUTA/OUTB; 4. this circuit layout is flexible.

An anti-fuse memory unit circuit, an array circuit and a reading and writing method are disclosed. The advantages of the device and method include: 1. the anti-fuse memory cell circuit is a pure combinational circuit, compared to time sequence circuit, after a delay of a certain time, this disclosed device closes all paths and stops the logic action of entire circuit, thus lowering the static power consumption to approximately 0; 2. this circuit constituted two positive feedback loops through the design of a switch and a logic calculation module, which enables its readout circuit to read 0 or 1 more reliably; 3. this circuit can eliminate a complicated timing sequence control part, even output the anti-fuse codes directly without latching the readout circuit output OUTA/OUTB; 4. this circuit layout is flexible.