An input facility for a controller or measurement apparatus includes at least one input circuit for providing at least one digital or at least one analog input for a controller or measurement apparatus, wherein the at least one input circuit includes at least one phase modulation converter that has an amplitude modulator with carrier suppression to which an input signal can be supplied on the input side in order to obtain a carrierless amplitude-modulated signal, an adder for adding a carrier signal shifted by 90 to the carrierless amplitude-modulated signal and for obtaining a phase-modulated signal, a limiter to which the phase-modulated signal is supplied and with which a noise amplitude modulation in the phase-modulated signal can be suppressed, and a demodulation facility to which the signal output from the limiter is supplied and that can be sampled therein with at least one sampling clock signal.

A test system includes a test and measurement instrument having one or more inputs for receiving one or more signals to be measured or tested, a display for outputting measurement results or test results, one or more processors for operating the instrument, a chassis housing the instrument, a power connection to receive power for powering the one or more processors from a wall connection. The test system further includes an external battery pack separate from the test and measurement instrument and structured to mechanically and electrically couple to and decouple from the test and measurement instrument, the external battery pack including a DC power source for powering the one or more processors. The test and measurement instrument includes no batteries or other power storage device for powering the one or more processors within the chassis of the instrument.

A test system implemented method removes intrinsic noise from a waveform representation of a repeating signal under test (SUT). The method includes obtaining an oversampled equivalent-time waveform representation of the repeating SUT. The method further includes obtaining a time-domain representation of a combined noise of the equivalent-time waveform above the deterministic maximum frequency by applying the equivalent-time waveform to a high-pass filter. The method further includes determining a standard deviation of the time-domain representation of the combined noise, and determining a correction factor in accordance with the standard deviation of the digitizer noise, and the standard deviation of the time-domain representation of the combined noise. The method further includes applying the equivalent-time waveform representation to a low-pass filter having a unity magnitude response at frequencies below the cutoff frequency and a correction factor magnitude response at frequencies above the cutoff frequency.

A digital signal processing method is for enhancing fidelity of equivalent-time waveform measurements. The method includes receiving a digitized equivalent-time waveform of a repeating signal under test (SUT), applying a low-pass filter to the digitized equivalent-time waveform to obtain a smoothed waveform, generating a residual waveform by subtracting the smoothed waveform from the digitized equivalent-time waveform, estimating contributions of multiple noise sources in the residual waveform using a regression model, computing target noise and jitter values by removing known intrinsic contributions, and reconstructing a corrected waveform by combining the smoothed waveform with a scaled version of the residual waveform, wherein the scaling is based on the target noise source contributions.

A test and measurement instrument has an input to receive a signal under test having a repeating pattern. one or more analog-to-digital converters (ADC) to sample the signal under test at a sample rate over many repeating patterns to digitize the signal, one or more processors configured to execute code to cause the one or more processors to: recover a clock from the sampled signal under test, use the clock to generate an original pattern waveform, interpolate and resample from the original pattern waveform to generate an evenly time-spaced pattern waveform, apply an equalizer to the evenly time-spaced pattern waveform to produce an equalized pattern waveform, interpolate and resample from the equalized pattern waveform to produce a new waveform having equalized samples at sample times of the sampled signal under test, recover an updated clock from the new waveform, and use the updated clock to produce an updated waveform.

The present disclosure provides a measurement application device comprising at least one signal acquisition interface configured to acquire an analog input signal and output a digital input signal, a first decimator for each signal acquisition interface, each one of the first decimators being configured to reduce the number of samples of the respective digital input signal and output a first decimated digital input signal, at least one second decimator for each signal acquisition interface, each one of the second decimators being configured to reduce the number of samples of the respective digital input signal and output a second decimated digital input signal, and at least one decoder for each one of the second decimators, each one of the decoders being configured to decode the respective second decimated digital input signal according to a respective protocol and provide a respective decoded input signal.

The disclosure relates to a method for controlling a test and/or measurement system which comprises a display unit configured to show a numerical control value of the test and/or measurement system. The method comprises activating a first editing mode of the test and/or measurement system, wherein in the first editing mode: a curser element is displayed at a predefined position with regards to the control value, and the control value is edited upon receiving a first user input. The method further comprises activating a second edition mode of the test and/or measurement system, wherein in the second editing mode: the position of the cursor element is moved to a digit of the control value, and a value of said digit is increased or decreased by a predefined step size upon receiving a second user input.

A test and measurement instrument includes two or more channels to allow the test and measurement instrument to connect to a device under test (DUT), each channel comprising an analog-to-digital converter (ADC) and one or more trigger engines, each trigger engine to determine one or more trigger conditions, a display to allow the test and measurement instrument to display data from the ADC, a user interface, and one or more processors configured to execute code to cause the one or more processors to acquire data from the two or more channels at a different time than others of the two or more channels in response to one or more trigger conditions. A test and measurement instrument similar to the above except it has at least one channel that has an auxiliary input and a threshold detector instead of an ADC in addition to one or more channels having ADCs.

A phase sequence indicator circuit includes first, second, and third phase inputs to receive first, second, and third alternating current (AC) phases of an input multiphase AC voltage. The phase sequence indicator circuit further includes a sequence detection circuit that includes phase sequence detection circuits. Each phase sequence detection circuit determines an order of the AC phases based on timing of one of the AC phases, and outputs a respective sequence indication signal. The phase sequence indicator circuit also includes an output circuit to determine whether the output sequence indication signals indicate a selected phase sequence for the input multiphase AC voltage.

The present disclosure relates to a probe adapter and a measurement system, including: a first interface, configured to be electrically connected to a probe; a second interface, configured to be electrically connected to a measuring instrument; signal transmission lines, including first and second signal transmission lines, and a line selection switch, where the first and second signal transmission lines are both located between the first interface and the second interface, and the line selection switch is configured to select the first signal transmission line or the second signal transmission line to conduct the first interface and the second interface; and a signal conditioning circuit, located on the second signal transmission line, and configured to adjust an impedance of a measured signal to match an input impedance of the measuring instrument, and/or adjust an amplitude of the measured signal to match a measurement range of the measuring instrument.