The present application provides a photovoltaic array test method and system, the method being applied to a photovoltaic array test system. The photovoltaic array test method comprises: obtaining the quantity of photovoltaic branches connected in a photovoltaic array; determining a reference electrical parameter according to the quantity of the photovoltaic branches and electrical parameters of the photovoltaic branches; if the photovoltaic array is electrically connected to the photovoltaic array test system, monitoring a test electrical parameter of the photovoltaic array; and determining a test result of the photovoltaic array according to the test electrical parameter and the reference electrical parameter.

There is provided a circuit for detecting a voltage fault. The circuit comprises filtering circuitry comprising a first time constant applicable to charging of the filtering circuitry and a second time constant different than the first time constant applicable to discharging of the filtering circuitry. The filtering circuitry filters input signals having a frequency greater than a threshold and passes input signals having a frequency less than the threshold. The circuit further comprises threshold detecting circuitry for determining whether signals output from the filtering circuitry exceeds a threshold voltage, wherein exceedance of the threshold voltage is indicative of the voltage fault.

A charger has a plurality of electrical interfaces, wherein a respective electrical interface is able to be coupled to an electrical energy store to be charged, in order to charge the electrical energy store to be charged. A common charge line of the charger carries a charging potential, in particular a positive charging potential, during the charging operation of the charger. A respective electrical interface includes: a first connection terminal which, when used as intended, is to be electrically connected to a corresponding connection terminal of an electrical energy store to be charged; two field-effect transistors which are looped-in in anti-serial fashion between the first connection terminal and the common charge line; and at least one control unit which is designed to drive the two field-effect transistors of a respective electrical interface such that, at any one time, the first connection terminal of only a single electrical interface is electrically connected to the common charge line via its two field-effect transistors.

There is provided a switch device, comprising a substrate; a p-n junction comprising a first p-doped layer provided on the substrate and a first n-doped layer provided on the substrate and opposing the first p-doped layer; a conduction layer provided on the substrate and extending from a first region adjacent the p-doped layer to a second region adjacent the n-doped layer, wherein the conduction layer comprises a plurality of charge carriers moveable within the conduction layer and wherein, in an initial state, the concentration of charge carriers in the first region is higher than in the second region; and wherein the first p-doped layer is vertically offset relative to the first n-doped layer to provide an offset region adjacent the first p-doped layer in which a plane parallel to the surface of the substrate extends through the offset region and the first n-doped layer; and wherein a part of the conduction layer defining at least a part of the first region is provided in the offset region such that an electric field generated by the p-n junction opposes the migration of the charge carriers from the first region to the second region.

[Problem] To implement a negative voltage monitoring circuit with high accuracy. [Solution] A negative voltage monitoring circuit includes a first voltage-dividing circuit, a first amplifier circuit, a second amplifier circuit, and an error determination circuit. The first voltage-dividing circuit divides a power supply voltage and outputs a first voltage. The first amplifier circuit is configured such that the first voltage is inputted to a noninverting input terminal and an output voltage is subjected to negative feedback. The second amplifier circuit is configured such that a second voltage is inputted to the noninverting input terminal, the second voltage being obtained by dividing a potential difference between the power supply voltage and a voltage to be monitored, the voltage being applied to an anode of a light receiving element, and an output voltage is subjected to negative feedback. The error determination circuit outputs an error signal on the basis of a difference between the output of the first amplifier circuit and the output of the second amplifier circuit.

A power pedestal includes: a pedestal member comprising a base structured to be attached to a platform and an enclosure extending from the base; a leakage current detection unit structured to detect a leakage current in the water in a slip and to output a leakage current detection signal based on the detected leakage current; and a marina safety status indication unit comprising: a control circuit connected to the leakage current detection circuit and structured to determine a real time marina safety status in the water within the slip and to output a marina safety status signal based on the determination; and a marina safety status indication device including a rub rail and a marina safety status indicator embedded in the rub rail and connected to the control circuit, the marina safety status indicator structured to provide the real time marina safety status based on the marina safety status signal.

This disclosure describes a driver circuit configured to control a gate injection transistor (GIT). The driver circuit is configured to output a control current to a gate of the GIT, detect a voltage at the gate of the GIT, and determine a load current through the GIT based on the voltage detected at the gate of the GIT. The voltage at the gate of the GIT may be dependent on both the load current and the control current.

A semiconductor integrated circuit includes: a high-side transistor as a PM OS transistor; and an overcurrent detection circuit comparing a current flowing the high-side transistor with a threshold current and including: a voltage-current conversion circuit converting a reference voltage into a reference current; a replica transistor as a PM OS transistor on a path of the reference current and including a source connected to a source of the high-side transistor; and a comparator comparing drain voltages of the high-side and replica transistors, wherein the voltage-current conversion circuit includes: an input terminal receiving the reference voltage; an NM OS transistor as a native transistor; a first resistor connected between a source of the NM OS transistor and a ground; and a voltage divider circuit including second and third resistors connected in series between the input terminal and the ground, and supplying a divided voltage of the reference voltage to a gate of the NM OS transistor.

The application relates to a light fixture comprising a compartment housing at least one light source configured to emit light in a main light emission direction. A lens is provided movably arranged relative to the light source in direction of the main light emission direction, and an electric motor configured to move the lens relative to the light source in direction of the main light emission direction. A control unit determines a current used by the electric motor to move the lens in the main light emission direction, wherein the control unit is configured to detect a presence of a liquid on the lens based on the determined current.

A method includes calculating a mismatch value between an input current associated with a master transistor of a current mirror circuit and a second current associated with a second transistor of the current mirror circuit, comparing the mismatch value to a predetermined mismatch threshold, and generating a comparison result that specifies whether the mismatch value exceeds the predetermined mismatch threshold. The parameter associated with the first transistor or the second transistor is modified when the mismatch value exceeds the predetermined mismatch threshold.